General description
The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs (I0 and I1) under control of a common data select input (S). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the true (non-inverted) form.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.

Features
* Wide supply voltage range from 1.65 V to 5.5 V
* High noise immunity
* Complies with JEDEC standard:
* JESD8-7 (1.65 V to 1.95 V)
* JESD8-5 (2.3 V to 2.7 V)
* JESD8B/JESD36 (2.7 V to 3.6 V)
* ±24 mA output drive (VCC = 3.0 V)
* CMOS low power consumption
* Latch-up performance exceeds 250 mA
* Direct interface with TTL levels
* Inputs accept voltages up to 5 V
* ESD protection:
* HBM JESD22-A114E exceeds 2000 V
* MM JESD22-A115-A exceeds 200 V
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVC1G157GW
74LVC1G157GV
74LVC1G157GM
74LVC1G157GF

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Features
*-25db Non-Adjacent Channel Crosstalk at 1.65Gbps
*Low Signal Loss: -1.5dBg attenuation at 1.65Gbps
*Isolation Ground Between Channels
*Fast Turn-on/off Time (< 6ns)
*1.65Gbps Throughput
*8kV ESD Protection
*Low Skew: Intra-pair <90ps, Inter-pair < 150ps
*Low Power Consumption (1μA Maximum)

Applications
*XGA and 720p DVI and HDMI Video Source Selection

Description
The FSHDMI08 is a wide-bandwidth switch designed for routing HDMI link data, clock, and the relevant DDC and CEC control signals that support the data rate up to 1.65Gbps per channel for UXGA resolution. Applications include LCD TVs, DVD, set-top boxes, and notebook designs with multiple digital video interfaces.
This switch allows the passage of HDMI link signals with ultra-low non-adjacent channel crosstalk and ultralow off isolation. This is critical to minimize ghost image between active video sources in video applications. The wide bandwidth of this switch allows the high-speed
differential signal to pass through with minimal additive skew and phase jitter. The pinout supports an HDMI Standard-A connector PCB layout.


FSHDMI08MTDX
FSHDMI08BQX

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Features
■ ICC and IOZ reduced by 50%
■ Multiplexer expansion by tying outputs together
■ Inverting 3-STATE outputs
■ Outputs source/sink 24mA
■ TTL-compatible inputs

General Description
 The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form.
 The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.

Functional Description
The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the I
0x inputs are selected and when Select is HIGH, the I1x inputs are selected.
 The data on the selected inputs appears at the outputs in inverted form. The ACT258 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:
Za= OE • (I1a • S + I0a • S)
Zb= OE • (I1b • S + I0b • S)
Zc= OE • (I1c • S + I0c • S)
Zd= OE • (I1d • S + I0d • S)
When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings.
 Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap.

74ACT258SC
74ACT258SJ
74ACT258MTC

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General Description
 Maxim’s DG508A and DG509A are monolithic CMOS analog multiplexers (muxes): the DG508A is a single 8-channel (1-of-8) mux, and the DG509A is a differential 4-channel (2-of-8) mux.
Both devices guarantee break-before-make switching. Maxim guarantees these muxes will not latch up if the power supplies are turned off with the input signals still present. Maxim also guarantees continuous operation when these devices are powered by supplies ranging from ±4.5V to ±18V.
 The DG508A/DG509A are plug-in upgrades for the industry- standard DG08A/DG509A, respectively. Maxim’s parts have lower on-resistance, faster enable switching times, and significantly lower leakage currents. The DG508A/ DG509A also consume significantly lower power, making them ideal for portable equipment.

Applications
* Control Systems
* Data Logging Systems
* Aircraft Heads-Up Displays
* Data-Acquisition Systems
* Signal Routing

Features
* Improved Second Source
* Operate from ±4.5V to ±18V Supplies
* Symmetrical, Bidirectional Operation
* Logic and Enable Inputs, TTL and
 - CMOS Compatible
* Latchup-Proof Construction
* Monolithic, Low-Power CMOS Design

DG508ACJ DG508ACWE DG508AC/D DG508ABK DG508ADJ DG508ADY DG508AEGE
DG508AEWE DG508AAK DG509A

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General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

Features
ㅁ Low ON resistance:
  * 80 W (typical) at VCC - VEE = 4.5 V
  * 70 W (typical) at VCC - VEE = 6.0 V
  * 60 W (typical) at VCC - VEE = 9.0 V
ㅁ Logic level translation:
  * To enable 5 V logic to communicate with ±5 V analog signals
ㅁ Typical ‘break before make’ built in
ㅁ Complies with JEDEC standard no. 7A
ㅁ ESD protection:
  * HBM EIA/JESD22-A114-C exceeds 2000 V
  * MM EIA/JESD22-A115-A exceeds 200 V
ㅁ Multiple package options
ㅁ Specified from -40 °C to +85 °C and from -40 °C to +125 °C


74HCT4053 74HC4053D 74HCT4053N 74HCT4053D 74HCT4053PW 74HCT4053BQ

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FEATURES
· Wide analog input voltage range: ± 5 V.
· Low “ON” resistance:
80 W (typ.) at VCC - VEE = 4.5 V
70 W (typ.) at VCC - VEE = 6.0 V
60 W (typ.) at VCC - VEE = 9.0 V
· Logic level translation:
to enable 5 V logic to communicate with ± 5 V analog
signals
· Typical “break before make” built in
· Output capability: non-standard
· ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4051 are high-speed Si-gate CMOS devices and are pin compatible with the “4051” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4051 are 8-channel analog multiplexers/demultiplexers with three digital select inputs (S0 to S2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). With E LOW, one of the eight switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are in the high impedance OFF-state, independent of S0 to S2. VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E). The VCC to GND ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The analog inputs/outputs (Y0 to Y7, and Z) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

74HCT4051 74HCU4051 74HCMOS4051

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General Description
The CD4051BC, CD4052BC, and CD4053BC analog multiplexers/ demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3−15V. For example, if VDD = 5V, VSS = 0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0−5V. The multiplexer circuits dissipate extremely low quiescent
power over the full VDD−VSS and VDD−VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. CD4051BC is a single 8-channel multiplexer having three binary control inputs. A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output. CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs. CD4053BC is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole double-throw configuration.

Features
ㅁWide range of digital and analog signal levels:
digital 3 – 15V, analog to 15Vp-p
ㅁLow “ON” resistance: 80Ω (typ.) over entire 15Vp-p signal-input range for VDD − VEE = 15V
ㅁHigh “OFF” resistance:
channel leakage of ±10 pA (typ.) at VDD − VEE = 10V
ㅁLogic level conversion for digital addressing signals of 3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals to 15 Vp-p (VDD − VEE = 15V)
ㅁMatched switch characteristics:
ΔRON = 5Ω (typ.) for VDD − VEE = 15V
ㅁVery low quiescent power dissipation under all digital-control input and supply conditions:
1 μ W (typ.) at VDD − VSS = VDD − VEE = 10V
ㅁBinary address decoding on chip

CD4052BC CD4053BC CD4051BCMTC CD4051BCN CD4052BCM CD4052BCSJ

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GENERAL DESCRIPTION
The ML2258 combines an 8-bit A/D converter, 8-channel analog multiplexer, and a microprocessor compatible 8- bit parallel interface and control logic in a single monolithic device. Easy interface to microprocessors is provided by the latched and decoded multiplexer address inputs and latched three-state outputs. The device is suitable for a wide range of applications from process and machine control to consumer, automotive, and telecommunication applications. The ML2258 is an enhanced, pin-compatible, second source for the industry standard ADC0808/ADC0809. The ML2258 enhancements are faster conversion time, true sample and hold function, superior power supply rejection, wider reference range, and a double buffered data bus as well as faster digital timing. All parameters are guaranteed over temperature with a power supply voltage of 5V ±10%.

FEATURES
ㅁ Conversion time 6.6μs
ㅁ Total unadjusted error ±1/2LSB or ±1LSB
ㅁ No missing codes
ㅁ Sample and hold 390ns acquisition
ㅁ Capable of digitizing a 5V, 50kHz sine wave
ㅁ 8-input multiplexer
ㅁ 0V to 5V analog input range with single 5V
power supply
ㅁ Operates ratiometrically or with up to 5V
voltage reference
ㅁ No zero-or full-scale adjust required
ㅁ Analog input protection 25mA per input min
ㅁ Low power dissipation 3mA max
ㅁ TTL and CMOS compatible digital inputs and outputs
ㅁ Standard 28-pin DIP or surface mount PCC
ㅁ Superior pin compatible replacement for ADC0808 and
ADC0809

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General Description
The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can
directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE® outputs. The design of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see ADC0816 data sheet. (See AN-247 for more information.)

Features
ㅁ Easy interface to all microprocessors
ㅁ Operates ratiometrically or with 5 VDC or analog span adjusted voltage reference
ㅁ No zero or full-scale adjust required
ㅁ 8-channel multiplexer with address logic
ㅁ 0V to 5V input range with single 5V power supply
ㅁ Outputs meet TTL voltage level specifications
ㅁ Standard hermetic or molded 28-pin DIP package
ㅁ 28-pin molded chip carrier package
ㅁ ADC0808 equivalent to MM74C949
ㅁ ADC0809 equivalent to MM74C949-1

Key Specifications
ㅁ Resolution
ㅁ Total Unadjusted Errorn Single Supply
ㅁ Low Power 15
ㅁ Conversion Time

ADC0809

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General Description
The 16:1 Mux selects one of sixteen inputs, E0 through E15, specified by four binary select inputs, A, B, C, and D. The true data is output on Y and the inverted data on W. Propagation
delays are the same for both inputs and addresses and are specified for 50 pF loading. Outputs conform to the standard 8 mA LS totem pole drive standard.

Features/Benefits
1. 24-pin SKINNYDIP saves space
2. Similar to 74150 (Fat DIP)
3. Low current PNP inputs reduce loading

DM74LS450 DM54LS450J DM74LS450J

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