General Description
The S70GL01GN00 is a 1024 Mbit, single power supply flash memory device organized as two S29GL512N dies in a single 64-ball Fortified-BGA package. Each S29GL512N die is 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 110 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide‚ on page 5 and the Ordering Information‚ on page 9. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE# or CE2#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

Software & Hardware Features
*Software features
- Program Suspend and Resume: read other sectors before programming operation is completed
- Erase Suspend and Resume: read/program other sectors before an erase operation is completed
- Data# polling and toggle bits provide status
- Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
*Hardware features
- Advanced Sector Protection
- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings
- Hardware reset input (RESET#) resets device
- Ready/Busy# output (RY/BY#) detects program or erase cycle completion

S70GL01GN00FAI010, S70GL01GN00FFI010, S70GL01GN00FAI020 S70GL01GN00FFI020, S70GL01GN00FAI120, S70GL01GN00FFI120 S70GL01GN00FAI012, S70GL01GN00FFI012, S70GL01GN00FAI022
S70GL01GN00FFI022, S70GL01GN00FAI122, S70GL01GN00FFI122
S70GL01GN00FAI013, S70GL01GN00FFI013, S70GL01GN00FAI023 S70GL01GN00FFI023, S70GL01GN00FAI123, S70GL01GN00FFI123

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Architectural Advantages
* Single power supply operation
- 3 volt read, erase, and program operations
* Manufactured on 0.23 um MirrorBit process technology
* SecSi™ (Secured Silicon) Sector region
- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence
- May be programmed and locked at the factory or by the customer
* Flexible sector architecture
- 256Mb: 512 32 Kword (64 Kbyte) sectors
- 128Mb: 256 32 Kword (64 Kbyte) sectors
- 64Mb (uniform sector models): 128 32 Kword (64 Kbyte) sectors or 128 32 Kword sectors
- 64Mb (boot sector models): 127 32 Kword (64 Kbyte) sectors + 8 4Kword (8Kbyte) boot sectors
- 32Mb (uniform sector models): 64 32Kword (64 Kbyte) sectors of 64 32Kword sectors
- 32Mb (boot sector models): 63 32Kword (64 Kbyte) sectors + 8 4Kword (8Kbyte) boot sectors
* Compatibility with JEDEC standards
- Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write protection
* 100,000 erase cycles typical per sector
* 20-year data retention typical

Performance Characteristics
* High performance
- 90 ns access time (128Mb, 64Mb, 32Mb), 100 ns access time (256Mb)
- 4-word/8-byte page read buffer
- 25 ns page read times (128Mb, 64Mb, 32Mb)
- 30 ns page read times (256Mb)
- 16-word/32-byte write buffer
- 16-word/32-byte write buffer reduces overall programming time for multiple-word updates
* Low power consumption (typical values at 3.0 V, 5 MHz)
- 18 mA typical active read current (64 Mb, 32 Mb)
- 25 mA typical active read current (256 Mb, 128 Mb)
- 50 mA typical erase/program current
- 1 μA typical standby mode current
* Package options
- 40-pin TSOP
- 48-pin TSOP
- 56-pin TSOP
- 64-ball Fortified BGA
- 48-ball fine-pitch BGA
- 63-ball fine-pitch BGA

Software & Hardware Features
* Software features
- Program Suspend & Resume: read other sectors before programming operation is completed
- Erase Suspend & Resume: read/program other sectors before an erase operation is completed
- Data# polling & toggle bits provide status
- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
- Unlock Bypass Program command reduces overall multiple-word programming time
* Hardware features
- Sector Group Protection: hardware-level method of preventing write operations within a sector group
- Temporary Sector Unprotect: VID-level method of charging code in locked sectors
- WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings on uniform sector models
- Hardware reset input (RESET#) resets device
- Ready/Busy# output (RY/BY#) detects program or erase cycle completion

S29GL256M
S29GL128M
S29GL064M
S29GL032M

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DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES
■ Single power supply operation
— 3 volt read, erase, and program operations
■ VersatileI/OTM control
— Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V
■ Manufactured on 0.23 µm MirrorBitTM process technology
■ SecSi™ (Secured Silicon) Sector region
— 128-doubleword/256-word sector for permanent, secure identification through an 8 doubleword/16-word random Electronic Serial Number, accessible through a command sequence
— May be programmed and locked at the factory or by the customer
■ Flexible sector architecture
— One hundred twenty-eight 32 Kdoubleword (64 Kword) sectors
■ Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection
■ 100,000 erase cycles per sector
■ 20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■ High performance
— 100 ns access time
— 30 ns page read times
— 0.5 s typical sector erase time
— 22 µs typical write buffer doubleword programming time: 16-doubleword/32-word write buffer reduces overall programming time for multiple-word updates
— 4-doubleword/8-word page read buffer
— 16-doubleword/32-word write buffer
■ Low power consumption (typical values at 3.0 V, 5 MHz)
— 26 mA typical active read current
— 100 mA typical erase/program current
— 2 µA typical standby mode current
■ Package options
— 80-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■ Software features
— Program Suspend & Resume: read other sectors before programming operation is completed
— Erase Suspend & Resume: read/program other sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
■ Hardware features
— Sector Group Protection: hardware-level method of preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of changing code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or erase cycle completion


GENERAL DESCRIPTION
 The Am29LV6402M consists of two 64 Mbit, 3.0 volt single power supply flash memory devices and is organized as 4,194,304 doublewords or 8,388,608 words. The device has a 32-bit wide data bus that can also function as an 16-bit wide data bus by using the WORD# input. The device can be programmed either in the host system or in standard EPROM programmers.

 An access time of 100 or 110 ns is available. Note that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and the Ordering Information sections. The device offered in an 80-ball Fortified BGA package. Each device
has separate chip enable (CE#), write enable WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition VCC input, a high-voltage accelerated program WP#/ACC) input provides shorter programming times through increased current. This feature is intended facilitate factory throughput during system production, but may also be used in the field if desired.

 The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.

 The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 oggle) status bits or monitor the Ready/Busy# RY/BY#) outputs to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead requiring only two write cycles to program data instead of four.

 The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options.
Hardware data protection measures include a low

 VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming
equipment.

 The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/ Program Resume feature enables the host system
to pause a program operation in a given sector to read any other sector and then complete the program operation.

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