DESCRIPTION
MB85RS256 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells.
MB85RS256 adopts the Serial Peripheral Interface (SPI).
The MB85RS256 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS256 can be used for 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS256 does not take long time to write data unlike Flash memories nor E2PROM, and MB85RS256 takes no wait time.

FEATURES
*Bit configuration : 32,768 words × 8 bits
*Operating power supply voltage : 3.0 V to 3.6 V
*Operating frequency : 15 MHz (Max)
*Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
*Operating temperature range : −20 °C to +85 °C
*Data retention : 10 years (+55 °C)
*High endurance : 10 Billion Read/writes
*Package : 8-pin plastic SOP (FPT-8P-M02)

MB85RS256PNF-G-JNE1, MB85RS256PNF-G-JN-ERE1
TAG CMOS, FRAM, Memory, SPI

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Description
The M25P10-A is a 1 Mbit (128 Kbit x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

Features
*1 Mbit of Flash memory
*Page Program (up to 256 bytes) in 1.4 ms (typical)
*Sector Erase (256 Kbit) in 0.65 s (typical)
*Bulk Erase (1 Mbit) in 1.7 s (typical)
*2.3 to 3.6 V single supply voltage
*SPI bus compatible serial interface
*50 MHz Clock rate (maximum)
*Deep Power-down mode 1 μA (typical)
*Electronic signatures
–JEDEC standard two-byte signature (2011h)
–RES instruction, one-byte signature (10h), for backward compatibility
*More than 20 years’ data retention
*Packages
–ECOPACK® (RoHS compliant)

M25P10-AVMN6TP/X, M25P10-AVMP6TP/X, M25P10-AVMB6TP/X

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Description
The CA3228 is a monolithic integrated circuit designed as an automotive speed-control system.
The system monitors vehicle speed and compares it to a stored reference speed. Any deviation in vehicle speed causes a servo mechanism to open or close the engine throttle as required to eliminate the speed error. The reference speed, set by the driver, is stored in a 9-bit counter.
The reference speed can be altered by the ACCEL and COAST driver commands. The ACCEL command causes the vehicle to accelerate at a controlled rate; the COAST command disables the servo, thereby forcing the vehicle to slowdown. Application of the brake disables the servo and places the system in the standby mode while the RESUME command returns the vehicle to the last stored speed.
Vehicle speed and driver commands are inputs to the integrated circuit via external sensors. Actuators are needed to convert the output signals into the mechanical action necessary to control vehicle speed.
The CA3228 is supplied in a 24 lead dual-in-line plastic package (E suffix). Refer to AN7326 for application information.

Features
*Low Power Dissipation
*I2L Control Logic
*Power-On Reset
*On-Chip Oscillator for System Time Reference
*Single Input Line for Operator Commands
*Amplitude Encoded Control Signals
*Transient Compensated Input Commands
*Controlled Acceleration Mode
*Internal Redundant Brake and Low-Speed Disable
*Braking Disable

Applications
*Automotive Speed Control
*Residential and Industrial Heating and Cooling Controls
*Industrial AC and DC Motor Speed Control
*Applications Requiring Acceleration and Deceleration Control

CA3228E

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GENERAL DESCRIPTION
W9812G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words × 4 banks × 16 bits. W9812G6IH delivers a data bandwidth of up to 200M words per second (-5). For different application, W9812G6IH is sorted into the following speed grades: -5/-6/-6C and -75. The –5 is compliant to the 200MHz/CL3 specification. The –6/-6C/-6I is compliant to the 166MHz/CL3 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the 133MHz/CL3 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G6IH is ideal for main memory in high performance applications.

FEATURES
*3.3V ± 0.3V Power Supply
*Up to 200 MHz Clock Frequency
*2,097,152 Words × 4 banks × 16 bits organization
*Self Refresh Mode
*CAS Latency: 2 and 3
*Burst Length: 1, 2, 4, 8 and full page
*Burst Read, Single Writes Mode
*Byte Data Controlled by LDQM, UDQM
*Auto-precharge and Controlled Precharge
*4K Refresh cycles / 64 mS
*Interface: LVTTL
*Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant

W9812G6IH-5, W9812G6IH-6, W9812G6IH-6C, W9812G6IH-6I, W9812G6IH-75

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General Description
The A29L160 is a 16Mbit, 3.0 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L160 is offered in 48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L160 can also be programmed in standard EPROM programmers.
The A29L160 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L160 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L160 also offers the ability to program in the Erase Suspend mode. The standard A29L160 offers access times of 70, 90 and 120ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE ) and output enable (OE ) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The A29L160 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L160 is fully erased when shipped from the factory. The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

Features
*Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors
*Access times:
- 70/90/120 (max.)
*Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
*Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors
*Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple program command sequence
*Top or bottom boot block configurations available
*Embedded Algorithms
- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
- Embedded Program algorithm automatically writes and verifies data at specified addresses
*Typical 100,000 program/erase cycles per sector
*20-year data retention at 125°C
- Reliable operation for the life of the system
*CFI (Common Flash Interface) compliant
- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
*Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply Flash memory standard
- Superior inadvertent write protection
*Data Polling and toggle bits
- Provides a software method of detecting completion of program or erase operations
*Ready / BUSY pin (RY / BY)
- Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP)
*Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
*Hardware reset pin (RESET )
- Hardware method to reset the device to reading array data
*Package options
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
- All Pb-free (Lead-free) products are RoHS compliant

A29L160TM-70, A29L160TV-70, A29L160TV-70F, A29L160TG-70, A29L160TM-90, A29L160TV-90, A29L160TG-90, A29L160TM-120, A29L160TV-120, A29L160TG-120

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Description
The AT29LV1024 is a 3-volt only in-system Flash programmable and erasable rea donly memory (PEROM). Its 1 megabit of memory is organized as 65,536 words by 16bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 50 mA. The device endurance issuch that any sector can typically be written to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29LV1024 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading f rom an EPROM. Reprogramming the AT29LV1024 is performed on a sector basis; 128 words of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 words of data are internally latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7 or I/O15. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Features
*Single Voltage, Range 3V to 3.6V Supply
*3-Volt Only Read and Write Operation
*Software Protected Programming
*Fast Read Access Time - 150 ns
*Low Power Dissipation
– 15 mA Active Current
– 50 μA CMOS Standby Current
*Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Sectors (128 words/sector)
– Internal Address and Data Latches for 128 Words
*Fast Sector Program Cycle Time - 20 ms
*Internal Program Control and Timer
*DATA Polling for End of Program Detection
*Typical Endurance > 10,000 Cycles
*CMOS and TTL Compatible Inputs and Outputs
*Commercial and Industrial Temperature Ranges

AT29LV1024-15JC, AT29LV1024-15TC, AT29LV1024-15JI, AT29LV1024-15TI, AT29LV1024-20JC, AT29LV1024-20TC, AT29LV1024-20JI, AT29LV1024-20TI, AT29LV1024-25JC, AT29LV1024-25TC, AT29LV1024-25JI, AT29LV1024-25TI
TAG Memory

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GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes.
The 8 bits of data appear on DQ0–DQ7.
The Am29F016D is offered in 48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD) form.
For more information, refer to publication number 21551.
This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply.
A 12.0 volt VPP is not required for program or erase operations.
The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.23 μm process technology, and offers all the features and benefits of the Am29F016, which was manufactured using 0.5 μm process technology.
The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states.
To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions.
Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commandsare written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence.
This initiates the Embedded Program algorithm-an internal algorithm that automatically
times the program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm-an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors.
The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions.
The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

DISTINCTIVE CHARACTERISTICS
*5.0 V ± 10%, single power supply operation
 -Minimizes system level power requirements
*Manufactured o 0.23 μm process technology
 -Compatible with 0.5 μm Am29F016 and 0.32 μm Am29F016B devices
*High performance
 -Access times as fast as 70 ns
*Low power consumption
 -25 mA typical active read current
 -30 mA typical program/erase current
 -1 μA typical standby current (standard access time to active mode)
*Flexible sector architecture
-32 uniform sectors of 64 Kbytes each
-Any combinatio of sectors ca be erased
-Supports full chip erase
-Group sector protection:
A hardware method of locking sector groups to prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code changes i previously locked sectors
*Embedded Algorithms
-Embedded Erase algorithm automatically preprograms and erases the entire chip or any  combinatio of designated sectors
-Embedded Program algorithm automatically writes and verifies bytes at specified addresses
*Unlock Bypass Program Command
-Reduces overall programming time whe issuing multiple program command sequences
*Minimum 1,000,000 program/erase cycles per sector guaranteed
*20-year data retentio at 125°C
-Reliable operatio for the life of the system
*Package options
-48-pi and 40-pi TSOP
-44-pi SO
-Know Good Die (KGD) (see publicatio number 21551)
*Compatible with JEDEC standards
-Pinout and software compatible with single-power-supply Flash standard
-Superior inadvertent write protection
*Data# Polling and toggle bits
-Provides a software method of detecting program or erase cycle completion
*Ready/Busy# output (RY/BY#)
-Provides a hardware method for detecting program or erase cycle completion
*Erase Suspend/Erase Resume
-Suspends a sector erase operatio to read data from, or program data to, a non-erasing sector,
the resumes the erase operation
*Hardware reset pi(RESET#)
-Resets internal state machine to the read mode

Am29F016D-70FI
Am29F016D-70E4C
Am29F016D-70F4E

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DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates.
Electrical erasure of the full memory contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard EPROM and E2PROM devices.
Programming and Erase are performed through an operation and verify algorithm.
The instructions are input via the I/O bus, using a two write cycle scheme.
Address and Data are latched to free the I/O bus and address bus during the write operation.
The CAT28F512 is manufactured using Catalyst’s advanced CMOS floating gate technology.
It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years.
The device is available in JEDEC approved 32-pin plastic DIP, 32-pin PLCC or 32-pin TSOP packages.

FEATURES
*Fast Read Access Time: 90/120/150 ns
*Low Power CMOS Dissipation:
-Active: 30 mA max (CMOS/TTL levels)
-Standby: 1 mA max (TTL levels)
-Standby: 100 mA max (CMOS levels)
*High Speed Programming:
-10 ms per byte
-1 Sec Typ Chip Program
*12.0V ± 5% Programming and Erase Voltage
*Electronic Signature
*Commercial, Industrial and Automotive Temperature Ranges
*Stop Timer for Program/Erase
*On-Chip Address and Data Latches
*JEDEC Standard Pinouts:
-32-pi*DIP
-32-pi*PLCC
-32-pi*TSOP ( 8 x 20)
*100,000 Program/Erase Cycles
*10 Year Data Retention

CAT28F512NI-90T
CAT28F512PI-90T
TAG CMOS, Memory

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GENERAL DESCRIPTION
The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 32 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
* 16 Mbit of Flash Memory
* Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB
* Bulk Erase (16 Mbit) in 20s (typical)
* Sector Erase (512 Kbit) in 1s (typical)
* Page Program (up to 256 Bytes) in 1.5ms (typical)
* 2.7 to 3.6V Single Supply Voltage
* SPI Bus Compatible Serial Interface
* 85MHz Clock Rate (maximum)
* Fast Read Dual Operation Instruction (3Bh/BBh)
* Deep Power-down Mode 1μA (typical)
* Top or Bottom Boot Block Configuration Available
* Electronic Signature
- JEDEC Standard Two-Byte Signature (2015h, Bottom;or 2025, Top)
- RES Instruction, One-Byte, Signature (14h)
* Package Options
- 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN
- All Pb-free (Lead-free) products are ROHS complaint

A2505PM-F
A2540PM-F
A2580PM-F
A2516PM-F
TAG Flash, Memory

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General Description
 The 24C32/ 24C64 provides 32,768/65,536 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 4096/8192 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where low power and low-voltage operation are essential.
The 24C32/ 24C64 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface.

Features
* Wide Voltage Operation
- VCC = 1.8V to 5.5V
* Operating Ambient Temperature: -40。C to +85。C
* Internally Organized:
- 24C32, 4096 X 8 (32K bits)
- 24C64, 8192 X 8 (64K bits)
* Two-wire Serial Interface
* Schmitt Trigger, Filtered Inputs for Noise Suppression
* Bidirectional Data Transfer Protocol
* 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
* Write Protect Pin for Hardware Data Protection
* 32-byte Page (32K, 64K) Write Modes
* Partial Page Writes Allowed
* Self-timed Write Cycle (5 ms max)
* High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
* 8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
* Die Sales: Wafer Form, Waffle Pack

24C64

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