General Description
The S29NS128J, S29NS064J, S29NS032J and S29NS016J are 128 Mbit, 64 Mbit, 32 Mbit and 16 Mbit 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 8,388,608, 4,194,304, 2,097,152 and 1,048,576. words of 16 bits each. These devices use a single VCC of 1.7 to 1.95 V to read, program, and erase the memory array. A 12.0-volt Acc may be used for faster program performance if desired. These devices can also be programmed in standard EPROM programmers.

Features
*Single 1.8 volt read, program and erase (1.7 to 1.95 V)
*Multiplexed Data and Address for reduced I/O count
– A15–A0 multiplexed as DQ15–DQ0
– Addresses are latched by AVD# control input when CE# low
*Simultaneous Read/Write operation
– Data can be continuously read from one bank while executing erase/program functions in other bank
– Zero latency between read and write operations
*Read access times at 54 MHz (CL=30 pF)
– Burst access times of 11/13.5 ns at industrial temperature range
– Asynchronous random access times of 65/70 ns
– Synchronous random access times of 71/87.5 ns
*Burst Modes
– Continuous linear burst
– 8/16/32 word linear burst with wrap around
– 8/16/32 word linear burst without wrap around
*Power dissipation (typical values, 8 bits switching, CL = 30 pF)
– Burst Mode Read: 25 mA
– Simultaneous Operation: 40 mA
– Program/Erase: 15 mA
– Standby mode: 9 μA
*Sector Architecture
– Four 8 Kword sectors
– Two hundred fifty-five (S29NS128J), one hundred twenty-seven (S29NS064J),sixty-three (S29NS032J), or thirty-one (S29NS016J) 32 Kword sectors
– Four banks (see next page for sector count and size)
*Sector Protection
– Software command sector locking
– WP# protects the two highest sectors
– All sectors locked when Acc = VIL
*Handshaking feature
– Provides host system with minimum possible latency by monitoring RDY
*Supports Common Flash Memory Interface (CFI)
*Software command set compatible with JEDEC 42.4 standards
– Backwards compatible with Am29F and Am29LV families
*Manufactured on 110 nm process technology
*Embedded Algorithms
– Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically writes and verifies data at specified addresses
*Data# Polling
– Provides a software method of detecting program and erase operation completion
*Erase Suspend/Resume
– Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
*Hardware reset input (RESET#)
– Hardware method to reset the device for reading array data
*CMOS compatible inputs and outputs
*Package
– 48-ball Very Thin FBGA (S29NS128J)
– 44-ball Very Thin FBGA (S29NS064J, S29NS032J, S29NS016J)
*Cycling Endurance: 1 million cycles per sector typical
*Data Retention: 20 years typical

S29NS128J0LBAW000, S29NS064J0LBAW000, S29NS032J0LBAW000

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Description
The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The NAND512R3A2C, NAND512R4A2C, NAND512W3A2C, and NAND512W4A2C have a density of 512 Mbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A Write Protect pin is available to give a hardware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the following packages:
*TSOP48 12 x 20mm
*VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch)
In order to meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
All devices have the Chip Enable Don't Care option, which allows the code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation.
A Serial Number option, allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.

Features
*High density NAND Flash memories
– 512 Mbit memory array
– Cost effective solutions for mass storage applications
*NAND interface
– x 8 or x 16 bus width
– Multiplexed Address/ Data
*Supply voltage: 1.8 V, 3.0 V
*Page size
– x 8 device: (512 + 16 spare) bytes
– x 16 device: (256 + 8 spare) words
*Block size
– x 8 device: (16 K + 512 spare) bytes
– x 16 device: (8 K + 256 spare) words
*Page Read/Program
– Random access: 12 μs (3 V)/15 μs (1.8 V) (max)
– Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)
– Page Program time: 200 μs (typ)
*Copy Back Program mode
*Fast Block Erase: 2 ms (typ)
*Status Register
*Electronic signature
*Chip Enable ‘don’t care’
*Serial Number option
*Hardware Data Protection
– Program/Erase locked during Power transitions
*Data integrity
– 100,000 Program/Erase cycles (with ECC)
– 10 years Data Retention
*ECOPACK® packages
*Development tools
– Error Correction Code models
– Bad Blocks Management and Wear Leveling algorithms
– Hardware simulation models

NAND512R4A2C, NAND512W3A2C, NAND512W4A2C

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