General Description
The S70GL01GN00 is a 1024 Mbit, single power supply flash memory device organized as two S29GL512N dies in a single 64-ball Fortified-BGA package. Each S29GL512N die is 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 110 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide‚ on page 5 and the Ordering Information‚ on page 9. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE# or CE2#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

Software & Hardware Features
*Software features
- Program Suspend and Resume: read other sectors before programming operation is completed
- Erase Suspend and Resume: read/program other sectors before an erase operation is completed
- Data# polling and toggle bits provide status
- Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
*Hardware features
- Advanced Sector Protection
- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings
- Hardware reset input (RESET#) resets device
- Ready/Busy# output (RY/BY#) detects program or erase cycle completion

S70GL01GN00FAI010, S70GL01GN00FFI010, S70GL01GN00FAI020 S70GL01GN00FFI020, S70GL01GN00FAI120, S70GL01GN00FFI120 S70GL01GN00FAI012, S70GL01GN00FFI012, S70GL01GN00FAI022
S70GL01GN00FFI022, S70GL01GN00FAI122, S70GL01GN00FFI122
S70GL01GN00FAI013, S70GL01GN00FFI013, S70GL01GN00FAI023 S70GL01GN00FFI023, S70GL01GN00FAI123, S70GL01GN00FFI123

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DESCRIPTION
Maxwell Technologies’ 28C010T high-density 1 Megabit (128K x 8-Bit) EEPROM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission.
The 28C010T is capable of in-system electrical byte and page programmability.
It has a 128-byte page programming function to make its erase and write operations faster.
It also features data polling and a Ready/Busy signal to indicate the completion of erase and programming operations.
In the 28C010T, hardware data protection is provided with the RES pin, in addition to noise protection on the WE signal and write inhibit on power on and off.
Software data protection is implemented using the JEDEC optional standard algorithm.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package.
It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK® provides greater than 100 krad(Si) radiation dose tolerance.
This product is available with screening up to Class S.

FEATURES
* 128k x 8-bit EEPROM
* RAD-PAK® radiation-hardened against natural space radiation
* Total dose hardness
- > 100 krad (Si), depending upon space mission
* Excellent Single event effects
- SELTH > 120 MeV/mg/cm2
- SEU > 90 MeV/mg/cm2 read mode
- SEU = 18 MeV/mg/cm2 write mode
* Package
- 32-pin RAD-PAK® flat pack/DIP package
- JEDEC-approved byte-wide pinout
* High speed
- 120, 150, and 200 ns maximum access times available
* High endurance
- 10,000 erase/write (in Page Mode),
- 10 year data retention
* Page write mode
- 1 to 128 bytes
* Low power dissipation
- 20 mW/MHz active (typical)
- 110 μW standby (maximum)
* Standard JEDEC package width

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FEATURES
• Single Voltage Read and Write Operations
– 5.0V-only for the SST29EE010A
– 3.0-3.6V for the SST29LE010A
– 2.7-3.6V for the SST29VE010A
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V
– Standby Current: 10 μA (typical)
• Fast Page Write Operation
– 128 Bytes per Page, 1024 Pages
– Page Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte Write Cycle Time: 39 μs (typical)
• Fast Read Access Time
– 5.0V-only operation: 90 and 120 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 20mm & 8mm x 14mm)

PRODUCT DESCRIPTION
The SST29EE010A/29LE010A/29VE010A are 128K x 8 CMOS Page Write EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE010A/29LE010A/29VE010A write with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE010A/29LE010A/ 29VE010A conform to JEDEC standard pinouts for bytewide memories.
Featuring high performance page write, the SST29EE010A/29LE010A/29VE010A provide a typical byte-write time of 39 μsec. The entire memory, i.e., 128 KBytes, can be written page-by-page in as little as 5 seconds, when using interface features such as Toggle
Bit or Data# Polling to indicate the completion of a write cycle. To protect against inadvertent write, the SST29EE010A/29LE010A/29VE010A have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST29EE010A/29LE010A/29VE010A are offered with a guaranteed page write endurance of
104 cycles. Data retention is rated at greater than 100 years.
The SST29EE010A/29LE010A/29VE010A are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST29EE010A/29LE010A/ 29VE010A significantly improve performance and reliability, while lowering power consumption. The SST29EE010A/29LE010A/29VE010A improve flexibility while lowering the cost for program, data, and configuration storage applications.
To meet high density, surface mount requirements, the SST29EE010A/29LE010A/29VE010A are offered in 32- pin TSOP and 32-lead PLCC packages. A 600-mil, 32- pin PDIP package is also available. See Figures 1 and 2 for pinouts.

SST29LE010A
SST29VE010A

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FEATURES
* Organized as 1M x16
* Dual-Bank Architecture for Concurrent Read/Write Operation
– 16 Mbit Bottom Sector Protection
- SST36VF1601: 12 Mbit + 4 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602: 4 Mbit + 12 Mbit
* Single 2.7-3.6V Read and Write Operations
* Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
* Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 4 μA (typical)
– Auto Low Power Mode: 4 μA (typical)
* Hardware Sector Protection/WP# Input Pin
– Protects 4 outer most sectors (4 KWord) in the larger bank by driving WP# low and unprotects by driving WP# high
* Hardware Reset Pin (RESET#)
– Resets the internal state machine to reading data array
* Sector-Erase Capability
– Uniform 1 KWord sectors
* Block-Erase Capability
– Uniform 32 KWord blocks
* Read Access Time
– 70 and 90 ns
* Latched Address and Data
* Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 μs (typical)
– Chip Rewrite Time: 8 seconds (typical)
* Automatic Write Timing
– Internal VPP Generation
* End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
* CMOS I/O Compatibility
* Conforms to Common Flash Memory Interface (CFI)
* JEDEC Standards
– Flash EEPROM Pinouts and command sets
* Packages Available
– 48-Pin TSOP (12mm x 20mm)
– 48-Ball TFBGA (8mm x 10mm)

PRODUCT DESCRIPTION
The SST36VF1601/1602 are 1M x16 CMOS Concurrent Read/Write Flash Memory manufactured with SST’s proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.The SST36VF1601/ 1602 write (Program or Erase) with a 2.7-3.6V power supply. The SST36VF1601/1602 devices conform to JEDEC standard pinouts for x16 memories.
Featuring high performance Word-Program, the SST36VF1601/1602 devices provide a typical Word-Program time of 14 μsec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the SST36VF1601/1602 devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST36VF1601/1602 devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.
The SST36VF1601/1602 are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST36VF1601/1602 significantly improve performance and reliability, while lowering power consumption.
The SST36VF1601/1602 inherently use less energy during Erase and Program than alternative flash technologies.
The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST36VF1601/1602 also improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST36VF1601/1602 are offered in 48-pin TSOP and 48- ball TFBGA packages. See Figures 3 and 4 for pinouts.

SST36VF1601-70-4C-EK
SST36VF1601-70-4C-BK
SST36VF1601-90-4C-EK
SST36VF1601-90-4C-BK

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DISTINCTIVE CHARACTERISTICS
■ 32 words sequential with wrap around (linear 32), bottom boot
■ One 8 Kword, two 4 Kword, one 48 Kword, three 64 Kword, and two 128 Kword sectors
■ Single power supply operation
— Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors
■ Read access times
Burst access times as fast as 17 ns at industrial temperature range (18 ns at extended temperature range) Initial/random access times as fast as 65 ns
■ Alterable burst length via BAA# pin
■ Power dissipation (typical)
— Burst Mode Read: 15 mA @ 25 MHz, 20 mA @ 33 MHz, 25 mA @ 40 MHz
— Program/Erase: 20 mA
— Standby mode, CMOS: 3 µA
■ 5 V-tolerant data, address, and control signals
■ Sector Protection
— Implemented using in-system or via programming equipment
— Temporary Sector Unprotect feature allows code changes in previously locked sectors
■ Unlock Bypass Program Command
— Reduces overall programming time when issuing multiple program command sequences
■ Embedded Algorithms
— Embedded Erase algorithm automatically preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes and verifies data at specified addresses
■ Minimum 100,000 erase cycle guarantee per sector
■ 20-year data retention
■ Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
— Backward-compatible with AMD Am29LV and
Am29F flash memories: powers up in asynchronous mode for system boot, but can immediately be placed into burst mode
■ Data# Polling and toggle bits
— Provides a software method of detecting program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device for reading array data
■ Package Option
— 56-pin SSOP

GENERAL DESCRIPTION
 The Am29BL802C is an 8 Mbit, 3.0 Volt-only burst mode Flash memory devices organized as 524, 288 words. The device is offered in a 56-pin SSOP package. These devices are designed to be programmed in-system with the standard system 3.0-volt VCC supply. A 12.0-volt VPP or 5.0 VCC is not required for program or erase operations. The device can also be programmed in standard EPROM programmers.
 The device offers access times of 65, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

Burst Mode Features
The Am29BL802C offers a Linear Burst mode—a 32 word sequential burst with wrap around—in a bottom boot configuration only. This devices require additional control pins for burst operations: Load Burst Address (LBA#), Burst Address Advance (BAA#), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations.

AMD Flash Memory Features
 Each device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The I/O and control signals are 5V tolerant.
 The Am29BL802C is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
 Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
 The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
 The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
 The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
 The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
 The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

AM29BL802CB-65RZI
AM29BL802CB-70RZI
AM29BL802CB-90RZI
AM29BL802CB-120RZI
AM29BL802CB-65RZE
AM29BL802CB-70RZE
AM29BL802CB-90RZE
AM29BL802CB-120RZE
AM29BL802CB-65RZF
AM29BL802CB-70RZF
AM29BL802CB-90RZF
AM29BL802CB-120RZF
AM29BL802CB-65RZK
AM29BL802CB-70RZK
AM29BL802CB-90RZK
AM29BL802CB-120RZK

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DISTINCTIVE CHARACTERISTICS
* Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with
high performance 3.3 volt microprocessors
* Manufactured on 0.35 mm process technology
— Compatible with 0.5 mm Am29LV400 device
* High performance
— Full voltage range: access times as fast as 80 ns
— Regulated voltage range: access times as fast as 70 ns
* Ultra low power consumption (typical values at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
* Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent any program or erase operations within
that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors
* Unlock Bypass Program Command
— Reduces overall programming time when issuing multiple program command sequences
* Top or bottom boot block configurations available
* Embedded Algorithms
— Embedded Erase algorithm automatically preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes and verifies data at specified addresses
* Minimum 1,000,000 write cycle guarantee per sector
* Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
* Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
* Data# Polling and toggle bits
— Provides a software method of detecting program or erase operation completion
* Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase cycle completion
* Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
* Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data

GENERAL DESCRIPTION
 The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.

 This device is manufactured using AMD’s 0.35 mm process technology, and offers all the features and benefits of the Am29LV400, which was manufactured using 0.5 mm process technology. In addition, the Am29LV400B features unlock bypass programming and in-system sector protection/unprotection.
The standard device offers access times of 70, 80, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

 The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

 Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence.
 This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

 The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved in-system or via programming equipment.

 The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

 AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

AM29LV400B Am29LV400BT70REC Am29LV400BB70REC Am29LV400BT80EC   
Am29LV400BB80EC Am29LV400BT90EC Am29LV400BB90EC Am29LV400BT120EC   
Am29LV400BB120EC Am29LV400BT70RFC Am29LV400BB70RFC Am29LV400BT80FC   
Am29LV400BB80FC Am29LV400BT90FC Am29LV400BB90FC

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