Description
The XCR3064A CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner™ CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 μA at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the patented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 1.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.0 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
The XCR3064A CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).
The XCR3064A CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BPMicrosystems, SMS, and others. The XCR3064A also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported.

Features
*Industry's first TotalCMOS™ PLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
*3V, In-System Programmable (ISP) using a JTAG interface
-On-chip superVoltage generation
-ISP commands include: Enable, Erase, Program, Verify
-Supported by multiple ISP programming platforms
-Four pin JTAG interface (TCK, TMS, TDI, TDO)
-JTAG commands include: Bypass, Idcode
*High speed pin-to-pin delays of 7.5 ns
*Ultra-low static power of less than 100 μA
*5V tolerant I/Os to support mixed Voltage systems
*100% routable with 100% utilization while all pins and all macrocells are fixed
*Deterministic timing model that is extremely simple to use
*Up to 12 clocks with programmable polarity at every macrocell
*Support for complex asynchronous clocking
*Innovative XPLA™ architecture combines high speed with extreme flexibility
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Logic expandable to 37 product terms
*Advanced 0.35μ E2CMOS process
*Security bit prevents unauthorized access
*Design entry and verification using industry standard and Xilinx CAE tools
*Reprogrammable using industry standard device programmers
*Innovative Control Term structure provides either sum terms or product terms in each logic block for:
-Programmable 3-state buffer
-Asynchronous macrocell register preset/reset
-Up to two asynchronous clocks
*Programmable global 3-state pin facilitates `bed of nails' testing without using logic resources
*Available in PLCC, VQFP, and Chip Scale BGA packages
*Industrial grade operates from 2.7V to 3.6V

XCR3064A-7VQ44C, XCR3064A-10VQ44C, XCR3064A-12VQ44C, XCR3064A-7PC44C

Trackback :: http://datasheetblog.com/trackback/2402

댓글을 달아 주세요 Comment

Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.
A total of two function blocks provide 750 usable gates.
Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz.

Features
*Lowest power 32 macrocell CPLD
*5.0 ns pin-to-pin logic delays
*System frequencies up to 200 MHz
*32 macrocells with 750 usable gates
*Available in small footprint packages
-48-ball CS BGA (36 user I/O pins)
-44-pin VQFP (36 user I/O)
-44-pin PLCC (36 user I/O)
*Optimized for 3.3V systems
-Ultra-low power operation
-5V tolerant I/O pins with 3.3V core supply
-Advanced 0.35 micron five layer metal EEPROM process
-Fast Zero Power™ (FZP) CMOS design technology
*Advanced system features
-In-system programming
-Input registers
-Predictable timing model
-Up to 23 available clocks per function block
-Excellent pin retention during design changes
-Full IEEE Standard 1149.1 boundary-scan (JTAG)
-Four global clocks
-Eight product term control terms per function block
*Fast ISP programming times
*Port Enable pin for dual function of JTAG ISP pins
*2.7V to 3.6V supply voltage at industrial temperature range
*Programmable slew rate control per macrocell
*Security bit prevents unauthorized access
*Refer to XPLA3 family data sheet (DS012) for architecture description

XCR3032XL-5VQ44C
XCR3032XL-10VQ44C

Trackback :: http://datasheetblog.com/trackback/1891

댓글을 달아 주세요 Comment

Features
• 192 macrocells in 12 logic array blocks (LABs)
• Eight dedicated inputs, 64 bidirectional I/O pins
• Advanced 0.65-micron CMOS technology to increase performance
• Programmable interconnect array
• 384 expander product terms
• Available in 84-pin HLCC, PLCC, and PGA packages

Functional Description
The CY7C341B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions.
The 192 macrocells in the CY7C341B are divided into 12 Logic Array Blocks (LABs), 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip.
The speed and density of the CY7C341B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality of 20-pin PLDs, the CY7C341B allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the CY7C341B reduces board space, part count, and increases system reliability.
Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8 macrocells are connected to I/O pins and eight are buried, while for LABs B, C, D, E, H, I, J, and K, four macrocells are connected to I/O pins and 12 are buried. Moreover, in addition to the I/O and buried macrocells, there are 32 single product term logic expanders in each LAB. Their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell.

CY7C341B-25HC CY7C341B-25HI CY7C341B-25JC CY7C341B-25RC CY7C341B-35HC CY7C341B-35JC CY7C341B-35RC

Trackback :: http://datasheetblog.com/trackback/404

댓글을 달아 주세요 Comment