Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.

Features
*Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
*Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
*Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)
*Meets OC-192 GR-253-CORE jitter specifications
*Dual clock inputs w/manual or automatically controlled hitless switching
*Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)
*Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
*LOL, LOS, FOS alarm outputs
*Digitally-controlled output phase adjust
*I2C or SPI programmable
*On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation
*Small size: 6 x 6 mm 36-lead QFN
*Pb-free, ROHS compliant

Applications
*SONET/SDH OC-48/OC-192 line cards
*GbE/10GbE, 1/2/4/8/10GFC line cards
*ITU G.709 and custom FEC line cards
*Optical modules
*Wireless basestations
*Data converter clocking
*xDSL
*SONET/SDH + PDH clock synthesis
*Test and measurement

Si5326A-B-GM, Si5326B-B-GM, Si5326C-B-GM

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Description
The HA-2556 is a monolithic, high speed, four quadrant, analog multiplier constructed in the Intersil Dielectrically Isolated High Frequency Process.
The voltage output simplifies many designs by eliminating the current-to-voltage conversion stage required for current output multipliers.
The HA-2556 provides a 450V/μs slew rate and maintains 52MHz and 57MHz bandwidths for the X and Y channels respectively, making it an ideal part for use in video systems.
The suitability for precision video applications is demonstrated further by the Y-Channel 0.1dB gain flatness to 5.0MHz, 1.5% multiplication error, -50dB feedthrough and differential inputs with 8μA bias current. The HA-2556 also has low differential gain (0.1%) and phase (0.1°) errors.
The HA-2556 is well suited for AGC circuits as well as mixer applications for sonar, radar, and medical imaging equipment.
The HA-2556 is not limited to multiplication applications only; frequency doubling, power detection, as well as many other configurations are possible.

Features
*High Speed Voltage Output . . . . . . . . . . . . . . . . . 450V/μs
*Low Multiplication Error . . . . . . . . . . . . . . . . . . . . . . . 1.5%
*Input Bias Currents . . . . . . . . . . . . . . . . . . . . . . . . . . .8μA
*5MHz Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . -50dB
*Wide Y-Channel Bandwidth . . . . . . . . . . . . . . . . . . 57MHz
*Wide X-Channel Bandwidth . . . . . . . . . . . . . . . . . . 52MHz
*VY 0.1dB Gain Flatness . . . . . . . . . . . . . . . . . . . . 5.0MHz
*Pb-free available (RoHS compliant)

Applications
*Military Avionics
*Missile Guidance Systems
*Medical Imaging Displays
*Video Mixers
*Sonar AGC Processors
*Radar Signal Conditioning
*Voltage Controlled Amplifier
*Vector Generators

HA9P2556-9, HA9P2556-9Z, HA1-2556-9

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Description
The PI6C3503 is a Low Power Frequency Multiplier with Spread Spectrum function to reduce EMI interference. The PI6C3503 provides a 1 time Spread Spectrum modulated output from a single clock source or a crystal. The PI6C3503 can reduce EMI at the clock output and it allows signifi cant system cost savings by reducing the number of circuit board layers ferrite beads and shielding that are traditionally required to pass EMI regulations.
Power down control is selectable through external logic state setting. The various and small package outlines can save board size and is easy for layout.
The PI6C3503 can be used in most portable devices with low power requirements like PDA, DSC, MFP, Media player, portable-TV, and LCM(LCD Panel Module).
PI6C3503 is one of Pericom clock products, if you have application need with clock input or output not specifi ed here, please contact with Pericom for further information or custom clock design.

Features
*Produces a 1 time spread spectrum clock signal from the input frequency.
*2.5 V or 3.3V power supply operation.
*Input frequency range from 13MHz to 30MHz.
*Frequency Spreading Ratio : +1.15% (Typical @15MHz output frequency)
*Modulation Rate : Fin/640
*Low power consumption design
*6-pin SOT-23, 6-pin TDFN, 8-pin TSSOP, and 8-pin SOIC Packages.

PI6C3503TE, PI6C3503ZCE, PI6C3503WE, PI6C3503LE

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Description
 The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance.
The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz.
The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis.
The device provides virtually any frequency translation combination across this operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface.
The Si5319 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.

Features
* Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz
* Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
* Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)
* Meets OC-192 GR-253-CORE jitter specifications
* Clock or crystal input with manual clock selection
* Clock output selectable signal format (LVPECL, LVDS, CML, CMOS)
* Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
* Supports various frequency translations for Synchronous Ethernet
* LOL, LOS alarm outputs
* I2C or SPI programmable
* On-chip voltage regulator for 1.8 V ±5%, 2.5 or 3.3 V ±10% operation
* Small size: 6 x 6 mm 36-lead QFN
* Pb-free, ROHS compliant

Applications
* SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards
* GbE/10GbE, 1/2/4/8/10GFC line cards
* ITU G.709 and custom FEC line cards
* Optical modules
* Wireless basestations
* Data converter clocking
* xDSL
* Synchronous Ethernet
* Test and measurement
* Discrete PLL replacement
* Broadcast video

Si5319A-C-GM
Si5319B-C-GM
Si5319C-C-GM

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