DESCRIPTION
 The UPD16803 is a monolithic dual H bridge driver circuit which uses N-channel power MOS FETs in its driver stage.
By employing the power MOS FETs for the output stage, this driver circuit has a substantially improved saturation voltage and power consumption as compared with conventional driver circuits that use bipolar transistors.
In addition, the drive current can be adjusted by an external resistor in a power-saving mode.
The UPD16803 is therefore ideal as the driver circuit of the 2-phase excitation, bipolar-driven stepping motor for the head actuator of an FDD.

FEATURES
• Low ON resistance (sum of ON resistors of top and bottom transistors)
- RON1 = 1.5 W TYP. (VM = 5.0 V)
- RON2 = 2.0 W TYP. (VM = 12.0 V)
• Low current consumption: IDD = 0.4 mA TYP.
• Stop mode function that turns OFF all output transistors
• Compact surface mount package: 20-pin plastic SOP (300 mil)

UPD16803GS

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Outline
This audio IC was developed for notebook PCs and allows major reduction of amp circuit board area. (To conform to PC98, includes built-in speaker drive amp, headphone amp, line amp. stereo/monaural switching, DC voltage control electronic volume, watchdog, logic control function.)

Features
* Speaker amp: Stereo BTL output 0.7W (when VCC = 5.0V, RL = 8½)
* Electronic volume control (-60 ~ +20dB). THD = 0.5% (when POUT = 300mW, RL = 8½)
- THD1 = 0.5% (when VOUT = 100mVrms, RL = 16½)
- THD2 = 0.1% (when VOUT = 1VmVrms, RL = 10k½)
* Line amp: Mixes 4 inputs ( 2ch signals and outputs on 3 outputs ( 2ch. Stereo/monaural switching possible on one line. THD = 0.1% (when VOUT = 1Vrms, RL = 10k½)
* Microphone amp: Switch pin selects 1 of 4 inputs
* Logic control: Speaker, headphone and line amp (including microphone amp and mix amp) logic controllable. Current consumption 300μA during power save mode.

QFP-80B

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FEATURES
*2.7- thru 12-V Single Supply or +3- thru +6-Dual Supply
*On-Resistance—rON: 14 ohm
*Fast Switching—tON: 28 ns—tOFF: 13 ns
*TTL, CMOS Compatible
*Low Leakage: 100 pA

BENEFITS
*Widest Dynamic Range
*Low Signal Errors and Distortion
*Break-Before-Make Switching Action
*Simple Interfacing

APPLICATIONS
*Precision Automatic Test Equipment
*Precision Data Acquisition
*Communication Systems
*Battery Powered Systems
*Computer Peripherals
*SDSL, DSLAM
*Audio and Video Signal Routing

DESCRIPTION
The DG417L/418L/419L are low voltage pin-for-pin compatible companion devices to the industry standard DG417/418/419 with improved performance Using BiCMOS wafer fabrication technology allows the DG417L/418L/419L to operate on single and dual supplies.
Single supply voltage ranges from 3 to 12 V while dual supply operation is recommended with +3 to +6 V.

Combining high speed (tON: 28 ns), flat rON over the analog signal range (6 ), minimal insertion lose (up to 100 MHz), and excellent crosstalk and off-isolation performance (-70 dB
at 1 MHz), the DG417L/418L/419L are ideally suited for audio and video signal switching.
The DG417L and DG418L respond to opposite control logic as shown in the Truth Table. The DG419L has an SPDT configuration.

DG417LDY
DG418LDY
DG417LDQ
DG418LDQ

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The HMXADC9225 is a radiation hardened monolithic, single supply, 12-bit, 20 MSPS, analog-to-digital converter with an on-chip, high performance sample-andhold amplifier. The HMXADC9225 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20 MSPS data rates, and guarantees no missing codes over the full operating temperature range.
The HMXADC9225 is fabricated on a radiation hardened SOI-IV Silicon On Insulator
(SOI) process with very low power consumption.
The input of the HMXADC9225 allows for easy interfacing to space and military imaging, sensor, and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets including singleended applications. The dynamic performance is excellent.
The sample-and-hold amplifier (SHA) is well suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and well beyond the Nyquist rate.
A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format.

FEATURES
* Monolithic 12-Bit, 20 MSPS A/D Converter
* Rad Hard: >500k Rad(Si) Total Dose
* Single +5 V Analog Supply
* Complete On-Chip S/H Amplifier
* Straight Binary Output Data
* 5V or 3.3V Digital and I/O Supply
* No Missing Codes Guaranteed
* Differential Nonlinearity Error: 0.4 LSB
* Signal-to-Noise and Distortion Ratio: 69.6 dB
* Spurious-Free Dynamic Range: –81 dB
* 28-Lead Ceramic Flat Pack

Mixed Signal Rad Hard Process
The HMXADC9225 is fabricated on space qualified SOI CMOS process. High-speed precision analog circuits are now combined with high-density logic circuits that can reliably withstand the harshest environments.

Space Qualified Package
The HMXADC9225 is packaged in a 28 lead ceramic flat pack.

Low Power
The HMXADC9225 at 345 mW consumes a fraction of the power of presently available in existing monolithic solutions.

Output Enable (OE)
The OE input allows user to put the tri-state digital outputs into a high impedance mode.

Dual Power Supply Capability
The HMXADC9225 uses a single +5 V power supply simplifying system power supply design. It also features a separate digital I/O power supply line to accommodate 3.3V and 5V logic families.

On-Chip Sample-and-Hold (SHA)
The versatile SHA input can be configured for either single-ended or differential inputs.


HMXADC9225NZG
HMXADC9225NZN

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Overview
The LA7605M is a flat panel display color TV signal-processing I2C bus controller IC that supports all the broadcast standards used worldwide.

Features
• VIF/SIF bloc
Adjustment-free VCO, 4-mode audio trap/audio bandpass filter, buzz canceller RF AGC/video level
• Single crystal color system : PAL and NTSC
• Black stretch, sharpness control with coring on/off control, built-in variable Y system filters
(Y-DL and chrominance trap)
• Chrominance bandpass filter, demodulation ratio/angle control, support for CbCr input
• VS, HS, and BGP outputs, C-sync output, FSC output
• Dynamic contrast control
• VIF, SIF, video, and sync separator circuits with superlative weak field and nonstandard signal characteristics
• Adjustment-free VIF/SIF, audio trap, and audio bandpass filters
• Horizontal resonator-less adjustment-free system
• Supply voltage : VCC = 5V

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FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 0.75ns through 7000ns
• Delay tolerance: 2% or 0.5ns
• Temperature stability: ±2% typical (-40C to 85C)
• Vdd stability: ±1% typical (3.0V-3.6V)
• Minimum input pulse width: 15% of total delay
• 14-pin Gull-Wing available as drop-in replacement for hybrid delay lines

FUNCTIONAL DESCRIPTION
 The 3D3220 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 700ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number.
 
 The 3D3220 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy. The all-CMOS 3D3220 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14-pin SOIC and 16-pin SOL packages.

APPLICATION NOTES
OPERATIONAL DESCRIPTION The 3D3220 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

OPERATING FREQUENCY
The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

 To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D3220 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH
 The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

 To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D3220 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

3D3220-xx
3D3220G-XX
3D3220D-xx
3D3220S-xx

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