GENERAL DESCRIPTION
The XR-2206 is a monolithic function generator integrated circuit capable of producing high quality sine, square, triangle, ramp, and pulse waveforms of high-stability and accuracy. The output waveforms can be both amplitude and frequency modulated by an external voltage. Frequency of operation can be selected externally over a range of 0.01Hz to more than 1MHz.
The circuit is ideally suited for communications, instrumentation, and function generator applications requiring sinusoidal tone, AM, FM, or FSK generation. It has a typical drift specification of 20ppm/°C. The oscillator frequency can be linearly swept over a 2000:1 frequency range with an external control voltage, while maintaining low distortion.

FEATURES
*Low-Sine Wave Distortion, 0.5%, Typical
*Excellent Temperature Stability, 20ppm/°C, Typ.
*Wide Sweep Range, 2000:1, Typical
*Low-Supply Sensitivity, 0.01%V, Typ.
*Linear Amplitude Modulation
*TTL Compatible FSK Controls
*Wide Supply Range, 10V to 26V
*Adjustable Duty Cycle, 1% TO 99%

APPLICATIONS
*Waveform Generation
*Sweep Generation
*AM/FM Generation
*V/F Conversion
*FSK Generation
*Phase-Locked Loops (VCO)

XR-2206P, XR-2206CP, XR-2206D

DESCRIPTION
The DAC7800, DAC7801 and DAC7802 are members of a new family of monolithic dual 12-bit CMOS multiplying Digital-to-Analog Converters (DACs). The digital interface speed and the AC multiplying performance are achieved by using an advanced CMOS process optimized for data conversion circuits. High stability on-chip resistors provide true 12-bit integral and differential linearity over the wide industrial temperature range of –40°C to +85°C.
The DAC7800 features a serial interface capable of clockingin data at a rate of at least 10MHz. Serial data is clocked edge triggered) MSB first into a 24-bit shift register and then latched into each DAC separately or simultaneously as required by the application. An asynchronous CLEAR control is provided for power-on reset or system calibration functions. It is packaged in a 16-pin 0.3" wide plastic DIP.
The DAC7801 has a 2-byte (8 + 4) double-buffered interface. Data is first loaded (level transferred) into the input registers in two steps for each DAC. Then both DACs are updated simultaneously. The DAC7801 features an asynchronous CLEAR control. The DAC7801 is packaged in a 24-pin 0.3"

FEATURES
*TWO DACs IN A 0.3" WIDE PACKAGE
*SINGLE +5V SUPPLY
*HIGH-SPEED DIGITAL INTERFACE:
-Serial—DAC7800
-8 + 4-Bit Parallel—DAC7801
-12-Bit Parallel—DAC7802
*MONOTONIC OVER TEMPERATURE
*LOW CROSSTALK: –94dB min
*FULLY SPECIFIED OVER –40OC TO +85OC

APPLICATIONS
*PROCESS CONTROL OUTPUTS
*ATE PIN ELECTRONICS LEVEL SETTING
*PROGRAMMABLE FILTERS
*PROGRAMMABLE GAIN CIRCUITS
*AUTO-CALIBRATION CIRCUITS

DAC7801, DAC7802, DAC7800KP, DAC7801KP, DAC7802KP

Description
The HFA5253 is a very high speed monolithic pin driver solution for high performance test systems. The device will switch at high data rates between two input voltage levels providing variable amplitude pulses. Slew Rate Control pins provide independent control over positive and negative slew rate allowing the customer to optimize the pin driver speed for their application. The output impedance is trimmed to achieve a precision 50Ω source for impedance matching.
Two differential ECL/TTL compatible inputs control the operation of the HFA5253, one controlling the VHIGH/VLOW switching and the other controlling the output’s highimpedance state. The HFA5253’s 800MHz data rate makes it compatible with today’s high-speed VLSI test systems and the +8V to -3V output swing satisfies the most stringent testing requirements of all common logic families.
The HFA5253 is manufactured in Harris’ proprietary complementary bipolar UHF-1 process.

Features
*High Digital Data Rate . . . . . . . . . . . . . . . . . . . . . 800MHz
*Very Fast Rise/Fall Times. . . . . . . . . . . . . . . . . . . . . 500ps
*Wide Output Range . . . . . . . . . . . . . . . . . . . . . +8V to -3V
*Precise 50Ω Output Impedance
*High Impedance, Three-State Output Control
*Slew Rate Control

Applications
*IC Tester Pin Electronics
*Pattern Generators
*Pulse Generators
*Level Comparator/Translator

HFA5253CB

Outline
These ICs were developed for STATIC-RAM (S-RAM) battery back-up, and have built-in switching circuit for main power supply and battery, back-up timing circuit and battery checker.
Power ON/OFF and momentary power interruptions can damage S-RAM data on equipment that contains an S-RAM. These ICs switch the S-RAM to back-up mode (CS signal makes S-RAM CE pin low and CE pin high)
when power supply voltage goes below a set voltage (detection voltage 4.2V typ., variable), preventing damage to data. Further, when power supply voltage drops, these ICs switch from main power supply to battery back-up (switching voltage 3.3V typ.). Then, when power supply voltage rises, they first switch the SRAM from battery back-up state to main power supply (switching voltage 3.3V typ.), and from back-up mode to normal mode (CS signal makes S-RAM CE pin high and CE pin low). These signal processes provide reliable protection against data damage. The CS signal also can absorb power supply chattering and roughness through the external capacitor.
There is a built-in battery checker to monitor the back-up battery voltage, and this circuit is turned ON/OFF by the control pin.

Features
*Battery back-up
-Low IC current consumption (loss current) 0.3μA typ.
-Drop voltage inside IC (input/output voltage difference) IO=10μA 0.2V typ.
-Reverse current (reverse leak current) 0.1μA max.
*Normal operation
MM1027
-Drop voltage inside IC (input/output voltage difference) IO=70mA 0.2V typ.
-Output voltage VCC=5V IO=10mA 4.8V typ.
-Current consumption D.CONT OPEN 3.0mA max.
-External transistor drive current 25mA typ.
MM1081
-Drop voltage inside IC (input/output voltage difference) IO=120mA 0.25V typ.
-Output voltage VCC=5V IO=120mA 4.75V typ.
-Current consumption 350μA max.
-External transistor drive current (for output current increase) 25mA typ.
-TC source current 3.0μA typ.
*Battery-Vcc switching voltage 3.3V typ.
*Detection voltage (CS, CS) variable 4.2V typ.
*Battery checker 1
-X type 2.70V typ.
-N type 2.50V typ.
*Battery checker 2
-X type 2.55V typ.
-N type 2.35V typ.

Applications
*IC memory cards (RAM cards)
*PCs, word processors
*Fax machines, photocopiers, other office equipment
*Other equipment with S-RAMs (equipment requiring back-up)

MM1081, MM1027XV, MM1027NV, MM1081XV, MM1027XF, MM1027NF, MM1027XD

FUNCTIONAL DESCRIPTION
The 3D3424 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. For each line, the delay time is given by:
TDn = T0 + An * TI
where T0 is the inherent delay, An is the delay address of the n-th line and TI is the delay increment (dash number). The desired addresses are shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The serial interface can also be used to enable/disable each delay line. The 3D3424 operates at 3.3 volts and has a typical T0 of 9ns. The 3D3424 is CMOS-compatible, capable of sourcing or sinking 4mA loads, and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC.

FEATURES
*Four indep’t programmable lines on a single chip
*All-silicon CMOS technology
*Low quiescent current (5mA typical)
*Leading- and trailing-edge accuracy
*Vapor phase, IR and wave solderable
*Increment range: 1ns through 300ns
*Delay tolerance: 3% or 2ns (see Table 1)
*Line-to-line matching: 1% or 1ns typical
*Temperature stability: ±1.5% typical (-40C to 85C)
*Vdd stability: ±0.5% typical (3.0V to 3.6V)
*Minimum input pulse width: 10% of total delay

3D3424-1, 3D3424-1.5, 3D3424-2, 3D3424-4, 3D3424-5, 3D3424-10, 3D3424-15
3D3424-20, 3D3424-40, 3D3424-50, 3D3424-100, 3D3424-200, 3D3424-300

FUNCTIONAL DESCRIPTION
The 3D7323 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains three matched, independent delay lines. Delay values can range from 6ns through 6000ns. The input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. The 3D7323 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7323 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Delay range: 6 through 6000ns
*Delay tolerance: 2% or 1.0ns
*Temperature stability: ±3% typ (-40C to 85C)
*Vdd stability: ±1% typical (4.75V to 5.25V)
* Minimum input pulse width: 20% of total delay
*14-pin DIP available as drop-in replacement for hybrid delay lines

DESCRIPTION
The 3D3701 Delay Line Oscillator product family consists of fixed-frequency CMOS integrated circuit oscillators. Each package contains a single oscillator, which is gated and can therefore be synchronized to an external signal. The device frequency can range from 0.3MHz through 100MHz. The 3D3701 has two outputs that are in phase when the oscillator is running. The 3D3701 is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC package.

FEATURES
*All-silicon, low-power CMOS technology
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Frequency range: 0.3MHz through 100MHz
*Frequency tolerance: 0.5% typical
*Temperature stability: ±1.5% typical (-40C to 85C)
*Vdd stability: ±0.5% typical (3.0V to 3.6V)
*14-pin DIP available as drop-in replacements for hybrid delay line oscillators

Outline
This IC functions in a variety of CPU systems and other logic systems to generate a reset signal and reset the system accurately during momentary interruption or lowering of power supply voltage.
It also has a built-in watchdog timer for operation diagnosis.
This prevents the system from running wild by generating an intermittent reset pulse during system mis-operation.

Features
*Built-in watchdog timer
*Low minimum operating voltage VCC=0.8V typ.
*Both positive and negative logic reset output can be extracted
*Accurate detection of drop in power supply voltage
*Detection voltage has hysteresis
*Few external parts 1 capacitor
*Timer monitoring time can be varied by using an external resistor

MM1075XD
MM1075XF

FUNCTIONAL DESCRIPTION
The 3D7521 is a monolithic CMOS Manchester Encoder.
The clock and data, present at the unit input, are combined into a single bi-phase-level signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition.
The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ).
All pins marked N/C must be left unconnected.
The all-CMOS 3D7521 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Encoder.
It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads.
It is offered in space saving surface mount 8-pin and 14-pin SOICs.
The 3D7521 Manchester Encoder samples the data input at the rising edge of the input clock.
The sampled data is used in conjunction with the clock rising and falling edges to generate the by-phase level Manchester code.

FEATURES
* All-silicon, low-power CMOS technology
* TTL/CMOS compatible inputs and outputs
* Vapor phase, IR and wave solderable
* Low ground bounce noise
* Maximum data rate: 50 MBaud

FUNCTIONAL DESCRIPTION
 The 3D7522 product family consists of monolithic CMOS Manchester Decoders.
The unit accepts at the RX input a bi-phase-level, embedded-clock signal.
In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition.
The recovered clock and data signals are presented on CLK and DATB, respectively, with the data signal inverted.
The operating baud rate (in MBaud) is specified by the dash number.
The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received.
Because the 3D7522 is not PLL-based, it does not require a long preamble in order to lock onto the received signal.
Rather, the device requires at most one bit cell before the data presented at the output is valid.
This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off.
The all-CMOS 3D7522 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Decoders.
It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads.
It is offered in space saving surface mount 8-pin and 14-pin SOICs.

FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Low ground bounce noise
• Maximum data rate: 50 MBaud
• Data rate range: ±15%
• Lock-in time: 1 bit

3D7522-0.5
3D7522-1
3D7522-5
3D7522-10
3D7522-20
3D7522-25
3D7522-50