DESCRIPTION
The GAL22LV10D, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

FEATURES
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-4 ns Maximum Propagation Delay
-Fmax = 250 MHz
-3 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
*3.3V LOW VOLTAGE 22V10 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
-I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C)
*ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*TEN OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION 22LV10D

GAL22LV10D-4LJ, GAL22LV10D-5LJ, GAL22LV10C-7LJ, GAL22LV10C-10LJ

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Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.5 ns Maximum Propagation Delay
-Fmax = 250 MHz
-2.5 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
-TTL-Compatible Balanced 8mA Output Drive
*3.3V LOW VOLTAGE 20V8 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
*ACTIVE PULL-UPS ON ALL PINS
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL20LV8D-3LJ, GAL20LV8D-5LJ, GAL20LV8D-7LJ

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General Description
The LP62S4096E-T is a low operating current 4,194,304-bit static random access memory organized as 524,288 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing.
Data retention is guaranteed at a power supply voltage as low as 2V.
*CE2 pin for CSP package only

Features
*Power supply range: 2.7V to 3.6V
*Access times: 55ns / 70ns (max.)
*Current: Very low power version: Operating: 30mA (max.), Standby: 10mA (max.)
*Full static operation, no clock or refreshing required
*All inputs and outputs are directly TTL-compatible
*Common I/O using three-state output
*Data retention voltage: 2V (min.)
*Available in 32-pin TSOP/TSSOP 36-ball CSP package

LP62S4096EV-55LLT, LP62S4096EX-55LLT, LP62S4096EU-55LLT

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GENERAL DESCRIPTION
The K6T2008V2A and K6T2008U2A families are fabricated by SAMSUNG¢s advanced CMOS process technology. The family support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery backup operation with low data retention current.

FEATURES
*Process Technology: TFT
*Organization: 256Kx8
*Power Supply Voltage
-K6T2008V2A Family: 3.0V~3.6V
-K6T2008U2A Family: 2.7V~3.3V
*Low Data Retention Voltage: 2V(Min)
*Three State Outputs
*Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F 48-FBGA-6.00x7.00

K6T2008V2A-B, K6T2008U2A-B, K6T2008V2A-F, K6T2008U2A-F

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GENERAL DESCRIPTION
The A25L016 is 16M bit Serial Flash Memory, with advanced write protection mechanisms,  ccessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 32 blocks, each containing 16 sectors. Each sector is composed of 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 8,192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
*Family of Serial Flash Memories
- A25L016: 16M-bit /2M-byte
*Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 60ms (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
*Page Program (up to 256 Bytes) in 0.8ms (typical)
*2.7 to 3.6V Single Supply Voltage
*Dual input / output instructions resulting in an equivalent lock frequency of 200MHz:
- Dual Output Fast Read Instruction
- Dual Input and Output Fast Read Instruction
*SPI Bus Compatible Serial Interface
*100MHz Clock Rate (maximum)
*Deep Power-down Mode 5μA (Max)
*16Mbit Flash memory
- Uniform 4-Kbyte sectors
- Uniform 64-Kbyte blocks
*Electronic Signatures
- JEDEC Standard Two-Byte Signature A25L016: (3015h)
- RES Instruction, One-Byte, Signature, for backward compatibility A25L016 (14h)
*Package options
- 8-pin SOP (209mil), 16-pin SOP (300mil), 8-pin DIP (300mil)
- All Pb-free (Lead-free) products are RoHS compliant

A25L016-F, A25L016-UF, A25L016M-F, A25L016M-UF, A25L016N-F, A25L016N-UF

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