Description
The Xc4010D and XC4013D are RAM-less, lower-cost versions of the XC4010 and XC4013. They are identical to the XC4010 and XC4013 in all respects, except for the missing on-chip RAM.
The XC4010D and XC4013D are available in most of the same PLCC, PQFP, and PGA packages as their corresponding XC4000 non-D equivalents. See page 2-70 for details.
The XC4010D and XC4013D are also pin-compatible with the XC5210 (see XC5200 Data Sheet for additional information). The XC5210 provides another possible cost-reduction path for lower-performance applications that do not use the XC4000D features like wide-decoders and carry logic.
For complete electrical specifications, see pages 2-47 through 2-55.
For a detailed description of the device features, architecture and configuration methods, see pages 2-9 through 2-45.
For a detailed list of package printouts, please use the cross-referance on page 2-70.
For package physical dimensions and thermal data, see Section 4.

Features
*Third Generation Field-Programmable Gate Array
–Abundant flip-flops
–Flexible function generators
–No on-chip RAM
–Dedicated high-speed carry-propagation circuit
–Wide edge decoders (four per edge)
–Hierarchy of interconnect lines
–Internal 3-state bus capability
–Eight global low-skew clock or signal distribution network
*Flexible Array Architecture
–Programmable logic blocks and I/O blocks
–Programmable interconnects and wide decoders
*Sub-micron CMOS Process
–High-speed logic and Interconnect
–Low power consumption
*Systems-Oriented Features
–IEEE 1149.1-compatible boundary-scan logic support
–Programmable output slew rate (2 modes)
–Programmable input pull-up or pull-down resistors
–12-mA sink current per output
–24-mA sink current per output pair
*Configured by Loading Binary File
–Unlimited reprogrammability
–Six programming modes
*XACT Development System runs on ’386/’486-type PC, Apollo, Sun-4, and Hewlett-Packard 700 series
–Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD
–Fully automatic partitioning, placement and routing
–Interactive design editor for design optimization
–288 macros, 34 hard macros, RAM/ROM compiler

XC4010D, XC4013D
TAG Array, cell, Logic

Trackback :: http://datasheetblog.com/trackback/2658

댓글을 달아 주세요 Comment

General Description
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions.
With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification.
FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage.
Table 5 shows FLEX 10KE performance for some common designs.
All performance values were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or chematic design file.

Features
* Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 30,000 to 200,000 typical gates (see Tables 1 and 2)
- Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
* System-level features
- MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (tSU and tCO) up to 212 MHz
- Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic

EPF10K50E
EPF10K50S
EPF10K100E
EPF10K130E
EPF10K200E

Trackback :: http://datasheetblog.com/trackback/1822

댓글을 달아 주세요 Comment

General Description
Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer the MultiCore architecture, which combines the strengths of LUT-based and product-term-based devices with an enhanced memory structure.
LUT-based logic provides optimized performance and efficiency for datapath, register-intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines.
LUT- and productterm-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20KC architecture uniquely suited for SOPC designs.
Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20KC device.
APEX 20KC devices include additional features such as enhanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry.

Features
* Programmable logic device (PLD) manufactured using a 0.15-μm alllayer copper-metal fabrication process
- 25 to 35% faster design performance than APEXTM 20KE devices
- Pin-compatible with APEX 20KE devices
- High-performance, low-power copper interconnect
- MultiCoreTM architecture integrating look-up table (LUT) logic and embedded memory
- LUT logic used for register-intensive functions
- Embedded system blocks (ESBs) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)
* High-density architecture
- 200,000 to 1 million typical gates (see Table 1)
- Up to 38,400 logic elements (LEs)
- Up to 327,680 RAM bits that can be used without reducing available logic

EP20K200C
EP20K400C
EP20K600C
EP20K1000C
TAG device, Logic

Trackback :: http://datasheetblog.com/trackback/1687

댓글을 달아 주세요 Comment

General Description
 The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop PCs.
The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well as Motherboard GLUE logic into a 128-pin package.
This is space saving solution on the motherboard resulting in lower cost.
The LPC47M172 also provides 13 general purpose pins, which offer flexibility to the system designer, and two Fan Tachometer Inputs.
The LPC47M172’s LPC interface supports LPC I/O and DMA cycles.
The LPC47M172 includes complete legacy I/O: a keyboard interface with AMITM BIOS; SMSC's true CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs; one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP.
The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures; in addition, it provides data overflow and underflow protection.
The SMSC’s patented advanced digital data separator allows for ease of testing and use.
The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP.
The LPC47M172 incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake up events as well as PME support.
The PCC supports multiple low power-down modes.
The LPC47M172 is ACPI 1.0b/2.0 compatible.
The Motherboard GLUE logic includes various power management logic; including generation of nRSMRST, Power OK signal generation, 5V main and standby reference generation.
There are also three LEDs to indicate power status and hard drive activity.
The translation circuit converts 3.3V signals to 5V signals.
Also included is SMBus main power well to resume power well isolation circuitry.
The LPC47M172 supports the ISA Plug-and-Play Standard register set (Version 1.0a).
The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M172 may be reprogrammed through the internal configuration registers.
There are up to 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels.
On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface.
The LPC47M172’s Enhanced Digital Data Separator does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area.
The LPC47M172 is register compatible with SMSC’s proprietary 82077AA core.

Product Features
* 3.3V Operation (5V tolerant)
* LPC Interface
- Multiplexed Command, Address and Data Bus
- Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems
* ACPI 1.0b/2.0 Compliant
* Programmable Wake-up Event Interface
* PC99a/PC2001 Compliant
* General Purpose Input/Output Pins (13)
* Fan Tachometer Inputs (2)
* Green and Yellow Power LEDs
* ISA Plug-and-Play Compatible Register Set
* Motherboard GLUE Logic
- 5V Reference Generation
- 5V Standby Reference Generation
- IDE Reset/Buffered PCI Reset Outputs
- Power OK Signal Generation
- Power Sequencing
- Power Supply Turn On Circuitry
- Resume Reset Signal Generation
- Hard Drive Front Panel LED
- Voltage Translation for DDC to VGA Monitor
- SMBus Isolation Circuitry
- CNR Dynamic Down Control
* 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core
- Supports One Floppy Drive
- Configurable Open Drain/Push-Pull Output Drivers
- Supports Vertical Recording Format
* 16-Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions
* Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
* 480 Address, Up to Eight IRQ and Three DMA Options
* Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates
- Programmable Precompensation Modes
* Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface
- Asynchronous Access to Two Data Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
* Serial Ports
- Two Full Function Serial Ports
- High Speed 16C550A Compatible UART with Send/Receive 16-Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
* Infrared Port
- Multiprotocol Infrared Interface
- 32-Byte Data FIFO
- IrDA 1.0 Compliant
- SHARP ASK IR
- HP-SIR
- 480 Address, Up to 15 IRQ and Three DMA Options
* Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port
- Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)
- ChiProtect Circuitry for Protection
- 960 Address, Up to 15 IRQ and Three DMA Options
* Interrupt Generating Registers
- Registers Generate IRQ1 – IRQ15 on Serial IRQ Interface.
* XOR-Chain Board Test
* 128 Pin MQFP Package, 3.2 mm Footprint

LPC47M172-NR

Trackback :: http://datasheetblog.com/trackback/1605

댓글을 달아 주세요 Comment

General Description
 Altera® ACEX 1K devices provide a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs.
LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
These elements make ACEX 1K suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation and microcontrollers, as required in high-performance communications applications.
Based on reconfigurable CMOS SRAM elements, the ACEX 1K architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components.
The advanced process and the low voltage requirement of the 2.5-V core allow ACEX 1K devices to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches.
The ability to reconfigure ACEX 1K devices enables complete testing prior to shipment and allows the designer to focus on simulation and design verification.
ACEX 1K device reconfigurability eliminates inventory management for gate array designs and test vector generation for fault coverage.
ACEX 1K device performance for some common designs.
All performance results were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file.

Features
* Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 10,000 to 100,000 typical gates
- Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity)
* Cost-efficient programmable architecture for high-volume applications
- Die size reductions via hybrid process
- Low cost solution for high-performance communications applications
* System-level features
- MultiVolt™ I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
- Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2 for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic.
- Operate with a 2.5-V internal supply voltage
- In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port
- ClockLock TM and ClockBoost TM options for reduced clock delay, clock skew, and clock multiplication
- Built-in, low-skew clock distribution trees
- 100% functional testing of all devices; test vectors or scan chains are not required
- Pull-up on I/O pins before and during configuration
* Flexible interconnect
- FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays
- Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)
- Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)
- Tri-state emulation that implements internal tri-state buses
- Up to six global clock signals and four global clear signals
* Powerful I/O pins
- Individual tri-state output enable control for each pin
- Open-drain option on each I/O pin
- Programmable output slew-rate control to reduce switching noise
- Clamp to V CCIO user-selectable on a pin-by-pin basis
- Supports hot-socketing
* Software design support and automatic place-and-route provided by Altera’s MAX+PLUS®
II development system for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations
* Flexible package options are available in 100 to 484 pins, including the innovative FineLine BGA TM packages
* Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic

EP1K10
EP1K30
EP1K50
EP1K100

Trackback :: http://datasheetblog.com/trackback/1602

댓글을 달아 주세요 Comment

General Description
 The PEELTM 16CV8 is a Programmable Electrically Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs.
The PEELTM 16CV8 offers the performance, flexibility, ease of design and production practicality needed by logic designers today.
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP packages with 25ns speed and power consumption as low as 37mA.
EE-Reprogrammability provides the convenience of instant reprogramming for development and reusable production inventory minimizing the impact of programming changes or errors. EEReprogrammability also improves factory testability, thus assuring the highest quality possible.
The PEELTM 16CV8 architecture allows it to replace over standard 20- pin PLDs (PAL, GAL, EPLD etc.).
ICT’s PEELTM 16CV8 can be programmed with existing 16CV8 JEDEC file.
Some programmers also allow the PEELTM 16CV8 to be programmed directly from PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files.
Additional development and programming support for the PEELTM16CV8 is provided by popular
third-party programmers and development software.
ICT also offers free PLACE development software.

Features
• Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
• CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
• Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
• Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
• Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
- Automatic programmer translation and JEDEC file translation software available for the most popular PAL devices

16CV8P-25
16CV8J-25
16CV8S-25
16CV8T-25

Trackback :: http://datasheetblog.com/trackback/1541

댓글을 달아 주세요 Comment

Description
 The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed
performance available in the PLD market.
High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.
An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section.
GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture.
As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products.
In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
- 3.0 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 75mA Typ Icc on Low Power Device
- 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 20-pin PAL® Devices with Full Function/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS

GAL16V8D-25LJ
GAL16V8D-25LS
GAL16V8D-15QPN

Trackback :: http://datasheetblog.com/trackback/1529

댓글을 달아 주세요 Comment

General Description
 The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture.
Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Features
* High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
* 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
* Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
* Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
* Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates
* 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
* PCI-compliant devices available
* Open-drain output option in MAX 7000S devices
* Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
* Programmable power-saving mode for a reduction of over 50% in each macrocell
* Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
* 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
* Programmable security bit for protection of proprietary designs
* 3.3-V or 5.0-V operation
– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
* Enhanced features available in MAX 7000E and MAX 7000S devices
– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
– Programmable output slew-rate control
* Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations

Trackback :: http://datasheetblog.com/trackback/1505

댓글을 달아 주세요 Comment

Features...
■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
■ High–density PLDs ranging from 600 to 10,000 usable gates
■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages
■ Hot–socketing support
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ Industrial temperature range
■ PCI compatible
■ Bus–friendly architecture including programmable slew–rate control
■ Open–drain output option
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable power–saving mode for a power reduction of over 50% in each macrocell
■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ Enhanced architectural features, including:
– 6 or 10 pin– or logic–driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Programmable output slew–rate control
■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)

General Description
MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.

EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A

Trackback :: http://datasheetblog.com/trackback/687

댓글을 달아 주세요 Comment

Features
■ Very high speed-10 MBit/s
■ Superior CMR-10 kV/µs
■ Double working voltage-480V
■ Fan-out of 8 over -40°C to +85°C
■ Logic gate output
■ Strobable output
■ Wired OR-open collector
■ U.L. recognized (File # E90700)

Applications
■ Ground loop elimination
■ LSTTL to TTL, LSTTL or 5-volt CMOS
■ Line receiver, data transmission
■ Data multiplexing
■ Switching power supplies
■ Pulse transformer replacement
■ Computer-peripheral interface

Description
 The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/ 2631 dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13mA (fan out of 8).
 An internal noise shield provides superior common mode rejection of typically 10kV/µs. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/µs. The HCPL-2611 has a minimum
CMR of 10 kV/µs.

HCPL-2601
HCPL-2611
HCPL-2630
HCPL-2631

Trackback :: http://datasheetblog.com/trackback/615

댓글을 달아 주세요 Comment