GENERAL DESCRIPTION
The KM416S1120D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG¢s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
*3.3V power supply
*LVTTL compatible with multiplexed address
*Dual banks operation
*MRS cycle with address key programs
-CAS Latency ( 2 & 3)
-Burst Length (1, 2, 4, 8 & full page)
-Burst Type (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*Burst Read Single-bit Write operation
*DQM for masking
*Auto & self refresh
*15.6us refresh duty cycle (2K/32ms)

KM416S1120DT-G/FC, KM416S1120DT-G/F6, KM416S1120DT-G/F7

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General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L16181, A67L06361 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/LD ), synchronous clock enable ( CEN ), byte write enables (BW1,BW2,BW3,BW4) and read/write (R/W).
Asynchronous inputs include the output enable (OE), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state.
Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded.
The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.

Features
*Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz)
*Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization
*Signal +3.3V ± 5% power supply
*Individual Byte Write control capability
*Clock enable ( CEN) pin to enable clock and suspend operations
*Clock-controlled and registered address, data and control signals
*Registered output for pipelined applications
*Three separate chip enables allow wide range of options for CE control, address pipelining
*Internally self-timed write cycle
*Selectable BURST mode (Linear or Interleaved)
*SLEEP mode (ZZ pin) provided
*Available in 100 pin LQFP package

A67L06361, A67L16181E-6.5, A67L16181E-7.5, A67L16181-8.5

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Description
All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.

Features
*3.3 V Power supply
*Clock frequency: 100 MHz/83 MHz
*LVTTL interface
*Single pulsed RAS
*2 Banks can operates simultaneously and independently
*Burst read/write operation and burst read/single write operation capability
*Programmable burst length: 1/2/4/8/full page
*2 variations of burst sequence
-Sequential (BL = 1/2/4/8/full page)
-Interleave (BL = 1/2/4/8)
*Programmable CAS latency: 1/2/3
*Byte control by DQMU and DQML
*Refresh cycles: 4096 refresh cycles/64 ms
*2 variations of refresh
-Auto refresh
-Self refresh

HM5216165TT-10H, HM5216165TT-12
TAG LVTTL, SDRAM

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