The IDT5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9306 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL.
The IDT5T9306 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

*Guaranteed Low Skew < 25ps (max)
*Very low duty cycle distortion < 125ps (max)
*High speed propagation delay < 1.75ns (max)
*Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
*Up to 1GHz operation
*Selectable inputs
*Hot insertable and over-voltage tolerant inputs
*3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface
*Selectable differential inputs to six LVDS outputs
*Power-down mode
*2.5V VDD
*Available in VFQFPN package

*Clock distribution

TAG Buffer, Clock, LVDS

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The ADN4663 is a dual, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 600 Mbps (300 MHz), and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals.
The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted-pair cable. The transmitted signal develops a differential voltage of typically ±355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level by a line receiver.
The ADN4663 and a companion receiver offer a new solution to high speed point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).

*±15 kV ESD protection on output pins
*600 Mbps (300 MHz) switching rates
*Flow-through pinout simplifies PCB layout
*300 ps typical differential skew
*700 ps maximum differential skew
*1.5 ns maximum propagation delay
*3.3 V power supply
*±355 mV differential signaling
*Low power dissipation: 23 mW typical
*Interoperable with existing 5 V LVDS receivers
*Conforms to TIA/EIA-644 LVDS standard
*Industrial operating temperature range (−40°C to +85°C)
*Available in surface-mount (SOIC) package

*Backplane data transmission
*Cable data transmission
*Clock distribution


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General Description
The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an onchip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm LLP package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.

*Dual Supplies: 1.8V and 3.0V operation
*On chip automatic calibration during power-up
*Low power consumption
*Multi-level multi-function pins for CLK/DF and PD
*Power-down and sleep modes
*On chip precision reference and sample-and-hold circuit
*On chip low jitter duty-cycle stabilizer

*High IF Sampling Receivers
*Multi-carrier Base Station Receivers GSM/EDGE, CDMA2000, UMTS, LTE and WiMax
*Test and Measurement Equipment
*Communications Instrumentation
*Data Acquisition
*Portable Instrumentation


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The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high performance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to both of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. Another mode allows loop back testing and allows the output of a PHY transmit pair to be routed to the PHY input pair. For examples, please refer to the Application Information section of the data sheet.
The ICS85454-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.

*Dual 2:1/1:2 MUX
*Three LVDS outputs
*Three differential inputs
*Differential inputs can accept the following differential levels: LVPECL, LVDS, CML
*Loopback test mode available
*Maximum output frequency: 2.5GHz
*Part-to-part skew: 250ps (maximum)
*Additive phase jitter, RMS: 0.05ps (typical)
*Propagation delay: 550ps (maximum)
*2.5V operating supply
*-40°C to 85°C ambient operating temperature
*Available in both standard and lead-free RoHS compliant packages

ICS85454AK-01, ICS85454AK-01T, ICS85454AK-01LF, ICS85454AK-01LFT

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The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408 provides a low power, low noise, low skew, point-to-point solution for distributing LVDS
clock signals.
Guaranteed output and part-to-part skew specifications make the ICS85408 ideal for those applications demanding well defined performance and repeatability.

*8 Differential LVDS outputs
*CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
*Maximum output frequency: 700MHz
*Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
*Translates any single-ended input signal to LVDS with resistor bias on nCLK input
*Multiple output enable inputs for disabling unused outputs in reduced fanout applications
*Output skew: 50ps (maximum)
*Part-to-part skew: 550ps (maximum)
*Propagation delay: 2.4ns (maximum)
*3.3V operating supply
*0°C to 70°C ambient operating temperature
*Lead-Free package RoHS compliant

ICS85408BG, ICS85408BGT

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 The ICS854054 is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.8GHz and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.
The ICS854054 has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels.
The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.
The select pins have internal pulldown resistors.
The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).

* High speed 4:1 differential multiplexer
* One differential LVDS output
* Four selectable differential clock inputs
* PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
* Maximum output frequency: 2.8GHz
* Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input
* Part-to-part skew: 375ps (maximum)
* Propagation delay: 700ps (maximum)
* Supply voltage range: 3.135V to 3.465V
* -40°C to 85°C ambient operating temperature
* Available in both standard and lead-free RoHS compliant packages


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· 3.3 V LVDS
· Output frequencies from 270-800 MHz
· Enable/Disable output for test and board debug
· -10/70 or –40/85 °C operating temperature
· Hermetically sealed ceramic SMD package
· Product is compliant to RoHS directive and fully compatible with lead free assembly

· Ethernet, Gigabit Ethernet
· Storage Area Network
· Digital Video
· Broadband Access

Vectron’s VCC6 Crystal Oscillator (XO) is quartz stabilized square wave generator with a LVDS
output, operating off a 3.3 volt supply.


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· >400 Mbps (200 MHz) Signaling Rates
· Flow-Through Pinout Simplifies PCB Layout
· 300 ps Maximum Differential Skew
· Propagation Delay Times 1.8 ns (Typical)
· 3.3 V Power Supply Design
· ±350 mV Differential Signaling
· High Impedance on LVDS Outputs on Power Down
· Conforms to TIA/EIA-644 LVDS Standard
· Industrial Operating Temperature Range (-40°C to 85°C)
· Available in SOIC and TSSOP Packages

The SN65LVDS047 is a quad differential linedriver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-W load when enabled.
The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100 W. The ransmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and  distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

TAG Driver, LVDS, Quad

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General Description
 The THC63LVDM83R transmitter converts 28bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. At a transmit clock frequency of 85MHz, 28bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 595Mbps per LVDS channel.
 Also available is THC63LVDM63R that converts 21bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. Both transmitters can be programmed reduced swing LVDS through a dedicated pin for low power consumption and EMI.

• 28:4 Data channel compression at up to 298 Megabytes per sec throughput
• Wide dot clock range: 20-85MHz suited for VGA, SVGA, XGA and SXGA
• Narrow bus (10 lines or 8 lines) reduces cable size
• Support Reduced swing LVDS for Low EMI
• 200mV swing LVDS/350mV swing LVDS selectable
• Support Spread Spectrum Clock Generator
• On chip Input Jitter Filtering
• PLL requires No external components
• Single 3.3V supply with 125mW(TYP)
• Power-Down Mode
• Low profile 56 or 48 Lead TSSOP Package
• Clock Edge Programmable
• Improved Replacement for the National DS90C383 or DS90C363


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