The CXK79M72C165GB (organized as 262,144 words by 72 bits) and the CXK79M36C165GB (organized as 524,288 words by 36 bits) are high speed CMOS synchronous static RAMs with common I/O pins. They are manufactured in compliance with the JEDEC-standard 209 pin BGA package pinouts defined for SigmaRAM™ devices. They integrate input registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Single Data Rate (SDR) Pipelined (PL) read operations and Double Late Write (DLW) write operations are supported, providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring source-synchronous operation.
All address and control input signals are registered on the rising edge of the CK input clock.
During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control signals are registered.
During write operations, input data is registered once, on the rising edge of CK, two full cycles after the address and control signals are registered.
Output drivers are series-terminated, and output impedance is selectable via the ZQ control pin. When ZQ is tied “low”, the impedance of the SRAM’s output drivers is set to ~25Ω. When ZQ is tied “high” or left unconnected, the impedance of the SRAM’s output drivers is set to ~50Ω.
333 MHz operation (333 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

*3 Speed Bins Cycle Time / Data Access Time
-3 3.0ns / 2.0ns
-33 3.3ns / 2.0ns
-4 4.0ns / 2.1ns
*Single 1.8V power supply (VDD): 1.7V or 1.75V (min) to 1.95V (max)
*Dedicated output supply voltage (VDDQ): 1.4V (min) to VDD (max)
*LVCMOS-compatible I/O interface
*Common I/O
*Single Data Rate (SDR) data transfers
*Pipelined (PL) read operations
*Double Late Write (DLW) write operations
*Burst capability with internally controlled Linear Burst address sequencing
*Burst length of two, three, or four, with automatic address wrap
*Full read/write data coherency
*Byte write capability
*Single-ended input clock (CK)
*Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2)
*Selectable output driver impedance via dedicated control pin (ZQ)
*Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)
*JTAG boundary scan (subset of IEEE standard 1149.1)
*209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package


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