Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.

Features
*Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
*Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
*Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)
*Meets OC-192 GR-253-CORE jitter specifications
*Dual clock inputs w/manual or automatically controlled hitless switching
*Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)
*Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
*LOL, LOS, FOS alarm outputs
*Digitally-controlled output phase adjust
*I2C or SPI programmable
*On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation
*Small size: 6 x 6 mm 36-lead QFN
*Pb-free, ROHS compliant

Applications
*SONET/SDH OC-48/OC-192 line cards
*GbE/10GbE, 1/2/4/8/10GFC line cards
*ITU G.709 and custom FEC line cards
*Optical modules
*Wireless basestations
*Data converter clocking
*xDSL
*SONET/SDH + PDH clock synthesis
*Test and measurement

Si5326A-B-GM, Si5326B-B-GM, Si5326C-B-GM

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Description
The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC-192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher than nominal SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is ideal for providing jitter attenuation in high performance timing applications.

Features
*Fixed frequency jitter attenuator with selectable clock ranges at 19, 38, 77, 155, 311, and 622 MHz (710 MHz max)
*Support for SONET, 10GbE, 10GFC, and corresponding FEC rates
*Ultra-low jitter clock output with jitter generation as low as 0.3 psRMS (50 kHz–80 MHz)
*Integrated loop filter with selectable loop bandwidth (100 Hz to 7.9 kHz)
*Meets OC-192 GR-253-CORE jitter specifications
*Dual clock inputs with integrated clock select mux
*One clock input can be 1x, 4x, or 32x the frequency of the second clock input
*Single clock output with selectable signal format: LVPECL, LVDS, CML, CMOS
*LOL, LOS alarm outputs
*Pin programmable settings
*On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation
*Small size (6 x 6 mm 36-lead QFN)
*Pb-free, RoHS compliant

Applications
*Optical modules
*SONET/SDH OC-48/OC-192 line cards
*10GbE, 10GFC line cards
*ITU G.709 line cards
*Wireless basestations
*Test and measurement

Si5316-B-GM

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Description
 The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance.
The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz.
The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis.
The device provides virtually any frequency translation combination across this operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface.
The Si5319 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.

Features
* Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz
* Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
* Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)
* Meets OC-192 GR-253-CORE jitter specifications
* Clock or crystal input with manual clock selection
* Clock output selectable signal format (LVPECL, LVDS, CML, CMOS)
* Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
* Supports various frequency translations for Synchronous Ethernet
* LOL, LOS alarm outputs
* I2C or SPI programmable
* On-chip voltage regulator for 1.8 V ±5%, 2.5 or 3.3 V ±10% operation
* Small size: 6 x 6 mm 36-lead QFN
* Pb-free, ROHS compliant

Applications
* SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards
* GbE/10GbE, 1/2/4/8/10GFC line cards
* ITU G.709 and custom FEC line cards
* Optical modules
* Wireless basestations
* Data converter clocking
* xDSL
* Synchronous Ethernet
* Test and measurement
* Discrete PLL replacement
* Broadcast video

Si5319A-C-GM
Si5319B-C-GM
Si5319C-C-GM

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GENERAL DESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for
use in PCI Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer.
In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5 multipliers, each of the two PCI Express™ outputs (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).

FEATURES
• Two 0.7V current mode differential HCSL output pairs
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Input frequency range: 90MHz - 140MHz
• VCO range: 450MHz - 700MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant packages
• Industrial temperature information available upon request

ICS9DB202CG
ICS9DB202CGT
ICS9DB202CGLF
ICS9DB202CGLFT
ICS9DB202CF
ICS9DB202CFT
ICS9DB202CFLF
ICS9DB202CFLFT

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