FEATURES
* Applications:
– Wave and pulse shapers
– Astable multivibrators
– Monostable multivibrators.
* Complies with JEDEC standard no. 7A
* ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
* Specified from -40 to +85 °C and -40 to +125 °C.

DESCRIPTION
 The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
 The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

74HCT14 74HC14D 74HCT14D 74HC14DB 74HCT14DB 74HC14N 74HCT14N 74HC14PW
74HCT14PW 74HC14BQ 74HCT14BQ

FEATURES
· Demultiplexing capability
· Multiple input enable for easy expansion
· Ideal for memory chip select decoding
· Active LOW mutually exclusive outputs
· Output capability: standard
· ICC category: MSI

GENERAL DESCRIPTION
The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The “138” features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter. The ”138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The ”138” is identical to the “238” but has inverting outputs.

GENERAL DESCRIPTION
The 74HC/HCT540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT540 are octal inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2.
A HIGH on OEn causes the outputs to assume a high impedance OFF-state.
The “540” is identical to the “541” but has inverting outputs.

FEATURES
· Inverting outputs
· Output capability: bus driver
· ICC category: MSI

74HC540, 74HCT540, 74HC540N, 74HCT540N, 74HC540B, 74HCT540B, 74HC540DB, 74HCT540DB