General description
The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

Features
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
* JESD8-12 (0.8 V to 1.3 V)
* JESD8-11 (0.9 V to 1.65 V)
+ JESD8-7 (1.2 V to 1.95 V)
+ JESD8-5 (1.8 V to 2.7 V)
+ JESD8-B (2.7 V to 3.6 V)
* ESD protection:
+ HBM JESD22-A114E Class 3A exceeds 5000 V
+ MM JESD22-A115-A exceeds 200 V
+ CDM JESD22-C101-C exceeds 1000 V
* Low static power consumption; ICC = 0.9 mA (maximum)
* Latch-up performance exceeds 100 mA per JESD 78 Class II
* Inputs accept voltages up to 3.6 V
* Low noise overshoot and undershoot < 10 % of VCC
* IOFF circuitry provides partial Power-down mode operation
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G386GW
74AUP1G386GM
74AUP1G386GF

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FEATURES
· Up to 20-A Output Current
· 4.75-V to 14-V Input Voltage
· Programmable Wide-Output Voltage (0.7 V to 3.6 V)
· Efficiencies up to 96%
· Digital I/O
– PWM signal
– INHIBIT
– Current limit flag (FAULT)
– Sychronous Rectifier Enable (SRE)
· Analog I/O
– Temperature
– Output currrent
· Safety Agency Approvals: (Pending)
– UL/IEC/CSA-C22.2 60950-1
· Operating Temperature: –40°C to 85°C

APPLICATIONS
· Digital Power Systems using UCD92XX Digital Controllers

DESCRIPTION
The PTD08A020W is a high-performance 20-A rated, non-isolated digital PowerTrain module. It is the power conversion section of a digital power system. The PTD08A020W must be used in conjunction with a digital power controller such as the UCD92XX or UCD91XX family. The PTD08A020W receives control signals from the digital controller and provides parametric and status information back to the digital controller. Together, PowerTrain modules and a digital power controller form a sophisticated, robust, and easily configured power management solution.
Operating from an input voltage range of 4.75 V to 14 V, the PTD08A020W provides step-down power conversion to a wide range of output voltages from, 0.7 V to 3.6 V. The wide input voltage range makes the PTD08A020W particularly suitable for advanced computing and server applications that utilize a loosely regulated 8-V to 12-V intermediate distribution bus. Additionally, the wide input voltage range increases design flexibility by supporting operation with tightly regulated 5-V, 8-V, or 12-V intermediate bus architectures.
The module incorporates output over-current and temperature monitoring which protects against most load faults. Output current and module temperature signals are provided for the digital controller to permit user defined over-current and over-temperature warning and fault scerarios.
The module uses double-sided surface mount construction to provide a low profile and compact footprint.
Package options include both through-hole and surface mount configurations that are lead (Pb) - free and RoHS compatible.
TAG Digital, Input

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Features
■ 1.65 to 3.6V inputs and outputs
■ High speed A outputs:
– tPD = 3.4ns at VCC = 3.0 to 3.6V
– tPD = 4.3ns at VCC = 2.3 to 2.7V
■ Symmetrical impedance A output:
– |IOH| = IOL = 12mA (Min) at VCC = 3.0V
– |IOH| = IOL = 8mA (Min) at VCC = 2.3V
■ High speed B outputs:
– tPD = 2.5ns (Max) at VCC = 3.0 to 3.6V
– tPD = 3.2ns (Max) at VCC = 2.3 to 2.7V
■ Symmetrical impedance A output:
– |IOH| = IOL = 24mA (Min) at VCC = 3.0V
– |IOH| = IOL = 18mA (Min) at VCC = 2.3V
■ Power down protection on inputs and outputs
■ 26Ω serie resistors in A port output
■ Operating voltage range:
– VCC(Opr) = 1.65V to 3.6V
■ Pin and function compatible with 54 SERIES H162245
■ Bus hold provided on both sides
■ Cold spare function
■ Latch-up performance exceeds 300mA (JESD 17)
■ ESD performance:
– HBM > 2000V (MIL STD 883 method 3015); MM > 200V
■ 300KRad Mil1019.6 Condition A, (RHA QML qualification extension undergone)
■ No SEL, no SEU under 72 Mev/cm2/mg LET heavy ions irradiation
■ QML qualified product
■ Device fully compliant with DSCC SMD 5962-02508

Description
The 54VCXH162245 is a low voltage CMOS 16 bit bus transceiver (3-state) fabricated with submicron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 1.65 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs.
This IC is intended for two-way asynchronous communication between data buses; the direction of data transmission is determined by DIR input.
The two enable inputs nG can be used to disable the device so that the buses are effectively isolated. The device circuits is including 26Ω series resistance in the A port outputs. These
resistors permit to reduce line noise in high speed applications. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor.
All inputs and outputs are equipped with protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess voltage. All floating bus terminals during High Z
State must be held HIGH or LOW.

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Features and Benefits
▪ 8 to 25 V input range
▪ Integrated DMOS switch
▪ Adjustable fixed off-time
▪ Adjustable output

Description
 The A8697 is a constant off-time current mode step-down regulator with a wide input voltage range. Regulation voltage is set by external resistors, to output voltages as low as 0.8 V.
The A8697 includes an integrated power DMOS switch to reduce the total solution footprint. It also features internal compensation, allowing users to design stable regulators with
minimal design efforts.

 The off-time can be set with an external resistor, allowing flexibility in inductor selection. Additionally, the A8697 has a logic level enable pin which can shut the device down and
put it into a low quiescent current mode for power sensitive applications.

 The A8697 is supplied in a low-profile 8-lead SOIC with exposed pad (package LJ). Applications include:
▪ Applications with 8 to 25 V input
▪ Consumer electronics, networking equipment
▪ 12 V lighter-powered applications (portable DVD, etc.)
▪ Point of Sale (POS) applications

A8697ELJTR-T
A8697ELJ-T

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Features
• 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at
65.536 Mbps or 32.768 Mbps or using a combination of rates
• 16,384 channel x 16,384 channel non-blocking digital TDM switch at 16.384 Mbps
• 8,192 channel x 8,192 channel non-blocking digital TDM switch at 8.192 Mbps
• High jitter tolerance with multiple input clock sources and frequencies
• Up to 64 serial TDM input streams, divided into 32 groups with 2 input streams per group
• Up to 64 serial TDM output streams, divided into 32 groups with 2 output streams per group
• Per-group input and output data rate conversion selection at 65.536 Mbps, 32.768 Mbps,
16.384 Mbps and 8.192 Mbps. Input and output data group rates can differ
• Per-group input bit delay for flexible sampling point selection
• Per-group output fractional bit advancement
• Two sets of output timing signals for interfacing additional devices
• Per-channel A-Law/µ-Law Translation
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per-stream Bit Error Rate (BER) test circuits
• Per-channel high impedance output control
• Per-channel force high output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16 bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for input and output timing
• IEEE 1149.1 (JTAG) test port
• 3.3 V I/O with 5V tolerant inputs; 1.8 V core voltage

Applications
• Large Switching Platforms
• Central Office Switches
• Wireless Base Stations
• Multi-service Access Platforms
• Media Gateways

Description
 The ZL50075 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a number of enhanced features, the ZL50075 is designed for high capacity voice and data switching applications.

 The ZL50075 has 64 input and 64 output data streams which can operate at 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full 32 K x 32 K channel switching capacity at bit rates of 65 Mbps and 32 Mbps. Up to 32 input and output data streams may operate at 65 Mbps. Up to 64 input and output data streams may operate at 32 Mbps, 16 Mbps or 8 Mbps. The data rate can be independently set in groups of 2 input or output streams. In this way it is possible to provide rate conversion from
input data channel to output data channel.

 The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams can independently reference their timings to the input clock or to the internal system clock.
The ZL50075 has a variety of user configurable options designed to provide flexibility when data streams are connected to multiple TDM components or circuits. These include:
• Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams connected through different data paths
• Two timing outputs, CKo1 - 0 and FPo1 - 0, which can be configured independently to provide a variety of clock and frame pulse options
• Support of both ST-BUS and GCI-Bus formats
- The ZL50075 also has a number of value added features for voice and data applications:
• Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity applications:
• Per-channel A-Law/µ-Law Conversions for both voice and data
• 64 separate Pseudo-random Bit Sequence (PRBS) test circuits; one per stream. This provides an integrated Bit
Error Rate (BER) test capability to facilitate data path integrity checking

 The ZL50075 has two major modes of operation: Connection Mode (normal) and Message Mode. In Connection Mode, data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping controlled by the Connection Memories. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and status information to external circuits or other TDM devices.

 A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and Control Registers used to program ZL50075 options. The port is configurable to interface with either 16 bit Motorola or Intel-type microprocessors.
The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.

ZL50075GAC
ZL50075GAG2

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Features
■ Low input offset voltage: 1.5mV max
■ Rail-to-rail input and output
■ Wide bandwidth 20MHz, stable for gain ≥3
■ Low power consumption: 1.1mA maximum
■ High output current: 35mA
■ Operating from 2.5V to 5.5V
■ Low input bias current, 1pA typ
■ ESD internal protection ≥ 5kV
■ Latch-up immunity

Description
 The TSV991/2/4 family of single, dual & quad operational amplifiers offers low voltage operation and rail-to-rail input and output.
 This family features an excellent speed/power consumption ratio, offering a 20MHz gainbandwidth, stable for gain above 3 (100pF capacitive load), while consuming only 1.1mA
max at 5V supply voltage. It also features an ultralow input bias current.
 These characteristics make the TSV991/2/4 family ideal for sensor interfaces, battery-supplied
and portable applications, as well as active filtering.

Applications
■ Battery-powered applications
■ Portable devices
■ Signal conditioning
■ Active filtering
■ Medical instrumentation

TSV992 TSV994
TAG GBP, Input

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The STR-A6259H is a 100 kHz PWM topology (with ±5% frequency jittering for minimum EMI) regulator specifically designed to satisfy the requirements for increased integration and reliability in flyback converters. It incorporates a primary control and drive circuit with an avalanche-rated power MOSFET.

 Covering the power range from below 17 watts for a 230 VAC input, or to 13 watts for a universal (85 to 264 VAC) input, this device can be used in a wide range of applications,
from DVD players and VCR player/recorders to ac adapters for cellular phones and digital cameras. An auto-burst standby function reduces power consumption at light load, while multiple protections, including the avalanche-energy guaranteed MOSFET, provide high reliability of system design.

 Cycle-by-cycle current limiting, undervoltage lockout with hysteresis, overvoltage protection, and thermal shutdown protect the power supply during the normal overload and fault conditions.
Overvoltage protection and thermal shutdown are latched after a short delay. The latch may be reset by cycling the input supply.

 Low start-up current and a low-power standby mode selected from the secondary circuit completes a comprehensive suite of features. It is provided in an 8-pin mini-DIP plastic package with pin 6 removed. The leadframe plating is pure Sb, and the package complies with RoHS.

FEATURES AND BENEFITS
•100 kHz PWM with ±5% frequency jittering for EMI noise filtering cost reduction
•Rugged 650 V avalanche-rated MOSFET:
- Simplified surge absorption
- No VDSS derating required
•Low RDS(on) : 6 Ω maximum
•Auto-burst mode for stand-by operation or light loads; less transformer audible noise
•Built-in leading edge blanking
•Soft start and low start-up current; start-up circuit disabled in operation
•Auto-burst stand-by (intermittent operation) input power <0.1 W at no load
•Built-in constant-voltage/constant current (CV/CC)
•Multiple protections:
- Pulse-by-pulse overcurrent protection (OCP)
- Overload protection (OLP) with auto restart
- Latching overvoltage protection (OVP)
- Undervoltage lockout (UVLO) with hysteresis
- Latching thermal shutdown (TSD)

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General Description
 The MAX1589 low-dropout linear regulator operates from a +1.62V to +3.6V supply and delivers a guaranteed 500mA continuous load current with a low 175mV dropout. The high-accuracy (±0.5%) output voltage is preset to internally trimmed voltages from +0.75V to 3.0V. An active-low, open-drain reset output remains asserted for at least 70ms after the output voltage reaches
regulation.
 This device is offered in 6-pin thin SOT23 and 6-pin 3mm x 3mm thin DFN packages. An internal PMOS pass transistor maintains low supply current, independent of load and dropout voltage, making the MAX1589 ideal for portable battery-powered equipment such as personal digital assistants (PDAs), digital still cameras, cell phones, cordless phones, and notebook computers. Other features include logic-controlled shutdown, short-circuit protection, and thermaloverload protection.

Features
* Low 1.62V Minimum Input Voltage
* Guaranteed 500mA Output Current
* ±0.5% Initial Accuracy
* Low 175mV Dropout at 500mA Load
* 70ms RESET Output Flag
* Supply Current Independent of Load and Dropout Voltage
* Logic-Controlled Shutdown
* Thermal-Overload and Short-Circuit Protection
* Preset Output Voltages (0.75V, 1.0V, 1.3V, 1.5V, 1.8V, 2.5V, and 3.0V)
* Tiny 6-Pin Thin SOT23 Package (<1.1mm High)
* Thin 6-Pin TDFN Package (<0.8mm High)

Applications
- Notebook Computers
- Cellular and PCS Telephones
- Personal Digital Assistants (PDAs)
- Hand-Held Computers
- Digital Still Cameras
- PCMCIA Cards
- CD and MP3 Players

MAX1589EZT
MAX1589ETA

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Description
 The MC10/100EP05 is a 2−input differential AND/NAND gate.
 The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest
AC performance available.
 The 100 Series contains temperature compensation.

Features
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• Pb−Free Packages are Available

MC10EP05D MC10EP05DG MC10EP05DR2 MC10EP05DR2G MC10EP05DT MC10EP05DTG
MC10EP05DTR2 MC10EP05DTR2G MC10EP05MNR4 MC10EP05MNR4G MC100EP05D
MC100EP05DG MC100EP05DR2 MC100EP05DR2G MC100EP05DT MC100EP05DTG
MC100EP05DTR2 MC100EP05DTR2G MC100EP05MNR4 MC100EP05MNR4G
TAG Input, NAND

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FEATURES
• Wide supply voltage: 1.2 to 3.6 V
• In accordance with JEDEC standard no. 8-1A.
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Output capability: standard
• ICC category: SSI

DESCRIPTION
The 74LVC27 is a high-performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
The 74LVC27 provides the 3-input NOR function.

74LVC27PWDH 74LVC27D 74LVC27DB 74LVC27PW

TAG Input, triple

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