Description
The HM62W1400H is a 4-Mbit high speed static RAM organized 4-Mword ´ 1-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W1400H is packaged in 400-mil 32-pin SOJ and 400-mil 32-pin TSOP II for high density surface mounting.

Features
*Single 3.3 V supply : 3.3 V ± 0.3 V
*Access time 12/15 ns (max)
*Completely static memory
-No clock or timing strobe required
*Equal access and cycle times
*Directly TTL compatible
-All inputs and outputs
*Operating current: 180/160 mA (max)
*TTL standby current: 60/50 mA (max)
*CMOS standby current: 5 mA (max) , 1 mA (max) (L-version)
*Data retension current: 0.6 mA (max) (L-version)
*Data retension voltage: 2 V (min) (L-version)
*Center VCC and VSS type pinout

HM62W1400HJP-12, HM62W1400HJP-15, HM62W1400HLJP-12, HM62W1400HLJP-15

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Description
The dual channel 5 Mb/s SFH6731 and SFH6732 high speed optocoupler consists of a GaAlAs infrared emitting diode, optically coupled with an integrated photo detector. The detector incorporates a Schmitt-Trigger stage for improved noise immunity. A Faraday shield provides a common mode transient immunity of 1000 V/μs at VCM = 50 V for SFH6731 and 500 V/μs at VCM = 300 V for SFH6732.
The SFH6731 and SFH6732 uses an industry standard DIP-8 package. With standard lead bending, creepage distance and clearance of ≥ 7.0 mm with lead bending options 6, 7 and 9 ≥ 8.0 mm are achieved.

Features
*Data Rate 5 MBits/s (2.5 MBit/s over Temperature)
*Buffer
*Isolation Test Voltage, 5300 VRMS
*TTL, LSTTL and CMOS Compatible
*Internal Shield for Very High Common Mode Transient Immunity
*Wide Supply Voltage Range (4.5 to 15 V)
*Low Input Current (1.6 mA to 5.0 mA)
*Specified from 0 °C to 85 °C
*Lead-free component
*Component in accordance to RoHS 2002/95/EC and WEEE 2002/96/EC

Applications
*Industrial Control
*Replace Pulse Transformers
*Routine Logic Interfacing
*Motion/Power Control
*High Speed Line Receiver
*Microprocessor System Interfaces
*Computer Peripheral Interfaces

SFH6731, SFH6732, SFH6732-X007

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Description and Applications
The TSS901E provides an interface between a Data-Strobe link - according to the IEEE Std 1355-1995 specification carrying a simple interprocessor communication protocol - and a data processing node consisting of a CPU and a communication and data memory.
The TSS901E offers hardware supported execution of the major parts of the interprocessor communication protocol: data transfer between two nodes of a multi-processor system is performed with minimal host CPU intervention. The TSS901E can execute simple commands to provide basic features for system control functions; a provision of fault tolerant features exists as well.
Although the TSS901E initial exploitation is for use in multi-processor systems where the high speed links standardisation is an important issue and where reliability is a requirement, it could be used in applications such as heterogeneous systems or modules without any communication feature like special image compression chips, some signal processors, application specific programmable logic or mass memory.
The TSS901E may also be used in single board systems where standardised high speed interfaces are needed and systems containing "non-intelligent" modules such as A/D-converter or sensor interfaces which can be assembled with the TSS901E thanks to the "control by link" feature.

Features
*3 identical bidirectional link channels allowing full duplex communication under selectable transmit rate from 1.25 up to 200 Mbit/s in each direction
*A COmmunication Memory Interface (COMI) provides autonomous accesses to a communication memory which are controlled by an arbitration unit, allowing two TSS901E to share one Dual Port Ram without external arbitration
*The scalable databus width (8/16/32 bit) allows flexible integration with any CPU type
*Little or big endian mode is configurable
*AHOst Control Interface (HOCI) gives read/write accesses to the TSS901E configuration registers and to the DS-link channels for the controlling CPU
*Device control via one of the three links allows its use in systems without a local controller
*Link disconnect detection and parity check at token (data and control) level; possible checksum generation for packet level check
*Power saving mode relying on automatic transmit rate reduction
*A user’s manual of the TSS901E (also called SMCS332) is available at:
http://www.spacewire.esa.int/tech/spacewire/products/index.htm
*Designed on Atmel MG1140E matrix and packaged into MQFPL196

TSS901EMA-E

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