'HCSL' related articles 1

  1. 2008/06/26 PI6C20800S - PCI Express 1:8 HCSL Clock Buffer
Description
PI6C20800S is a PCI Express, high-speed, low-noise differential clock buffer designed to be a companion to PI6C410BS PCIExpress clock generator for Intel server chipsets.
The device distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is LOW.
The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA.
When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated.
When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

Features
* Phase jitter fi lter for PCIe application
* Eight Pairs of Differential Clocks
* Low skew < 50ps
* Low Cycle-to-cycle jitter < 50ps
* Output Enable for all outputs
* Outputs Tristate control via SMBus
* Power Management Control
* Programmable PLL Bandwidth
* PLL or Fanout operation
* 3.3V Operation
* Packaging (Pb-Free & Green):
- 48-Pin SSOP (V)
- 48-Pin TSSOP (A)

PI6C20800SVE
PI6C20800SAE
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