• Low-cost HC05 core
• 16-pin PDIP, 16-pin SOIC package, or 20-pin SSOP
• 928 bytes of user ROM, including eight bytes of user vectors
• 64 bytes of user RAM
• Low-power operation at 1.8 V — VDD minimum (EEPROM read only)
• 128 bits of personality EEPROM (not memory mapped) programmed using CPU software or with on-chip serial programming ROM
• On-chip charge pump for in-circuit programming of the personality EEPROM at 2.7 to 5.5 Vdc
• 8-bit free-running timer
• 4-stage selectable real-time interrupt generator
• 10 bidirectional input/output (I/O) lines including:
– 8-mA sink capability on four I/O pins (PA7–PA4)
– Mask option for software programmable pulldowns on all I/O pins
– Mask option for port interrupts on four I/O pins (PA3–PA0) (keyboard scan feature)
• IRQ interrupt hardware mask, flag bit, and request bit
• Mask option for sensitivity on IRQ interrupt (edge- and level-sensitive or edge-sensitive only)
• On-chip oscillator (mask options for crystal/ceramic resonator oscillator with internal 2-MW resistor and 2-pin or 3-pin resistor capacitor (RC) oscillator)
• Mask option for reduced startup delay time with RC oscillator options
• Mask option for computer operating properly (COP) watchdog system
• Power-saving stop mode and wait mode instructions
• Mask option to convert STOP instruction to halt mode
• Illegal address reset
• Internal steering diode and pullup resistor on RESET pin to VDD
• Internal RESET pin pulldown from COP watchdog and ILADR

Mask Options
The MC68HC05K3 contains these eight mask options:
1. COP watchdog timer (enable or disable)
2. IRQ triggering (edge-sensitive or edge- and level-sensitive)
3. Port A interrupts (enable or disable)
4. Port software programmable pulldowns (enable or disable)
5. STOP instruction (enable or disable)
6. Oscillator type (crystal/ceramic resonator or RC)
7. RC oscillator type (2-pin or 3-pin)
8. RC oscillator startup delay (4064 or 16 f cycles)

 The MC68HC05K3 has a 1024-byte memory map. Therefore, it uses only the lower 10 bits of the address bus. In the following discussion, the upper six bits of the address bus can be ignored. Also, by using a mask option, the STOP instruction can be converted from acting as the normal
STOP instruction.
 The stack area also is reduced to 32 bytes due to the limited amount of RAM. Therefore, the stack pointer is reduced to only five bits, only decrements down to $00E0, and then wraps around to $00FF. All other instructions and registers behave as described in M6805 HMOS/M146805 CMOS Family User’s Manual,Motorola document order number M6805UM/AD3.

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The MC68HC908AB32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs) with embedded EEPROM for user data storage. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.

Features of the MC68HC908AB32 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• Memory map and pin functions compatible with MC68HC08AB32 and MC68HC08AB16
• 8-MHz internal bus frequency
• 32K-bytes user program FLASH memory with security1 feature
• 512 bytes of on-chip EEPROM with security feature
• 1K-byte of on-chip RAM
• Clock generator module (CGM)
• Two 16-bit, 4-channel timer interface modules (TIMA and TIMB) with selectable input capture, output compare, and PWM capability on each channel
• Programmable interrupt timer (PIT)
• Serial peripheral interface module (SPI)
• Serial communications interface module (SCI)
• 8-channel. 8-bit analog-to-digital converter (ADC)
• Low-power design (fully static with STOP and WAIT modes)
• Master reset pin and power-on reset
• 51 general-purpose input/output (I/O) pins:
– 30 shared-function I/O pins
– 5-bit keyboard wakeup port
– Selectable pullups on inputs on port D and port F
• System protection features
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset
– Illegal opcode detection with optional reset
– Illegal address detection with optional reset
• 64-pin quad flat pack (QFP)

Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit Index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 ´ 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support


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