Description
The Harris CD22402 (Note) is a CMOS LSI sync generator that produces all the timing signals required to drive a fully 2-to-1 interlaced 525-line 30-frame/second, or 625-line 25-frame/second TV camera or video processing system. A complete sync waveform is produced which begins each field with six serrated vertical sync pulses, preceded and followed by six half-width double frequency equalizing pulses. The sync output is gated by the master clock to preserve horizontal phase continuity during the vertical interval.
The CD22402 can be operated either in “genlock” mode, in which it is synchronized with a reference sync pulse train from another TV camera, or in “stand-alone” mode, in which it is synchronized with a local on-chip crystal oscillator (the crystal and two passive components are off chip). Also, the circuit can sense the presence or absence of a reference sync pulse train and automatically select the “genlock” or “stand-alone” mode.
A frame sync pulse is produced at the beginning of every odd field. The vertical counter can be reset to either the first equalizing pulse or the first vertical sync pulse of the vertical interval. The interlaced sync provided by the CD22402 differs from RS-170 by having slightly narrower sync and equalizing pulses. The clock frequency of 32 times horizontal rate allows for approximately 4ms horizontal pulse widths and 2ms equalizing pulses. Otherwise operation can be phase locked to a color sub-carrier for a full interlaced operating system.
The CD22402 is operable with a single supply over a voltage range of 4V to 15V.

Features
*Interlaced Composite Sync Output
*Automatic Genlock Capability
*Crystal Oscillator Operation
*525 or 625 Line Operation
*Vertical Reset Option
*Wide Power Supply Operating Voltage . . . . . 4V to 15V

Applications
*Cameras
*Monitors and Displays
*CATV
*Teletext
*Video Games
*Sync Restorer
*Video Service Instruments

CD22402D, CD22402E

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GENERAL DESCRIPTION
The XR-2206 is a monolithic function generator integrated circuit capable of producing high quality sine, square, triangle, ramp, and pulse waveforms of high-stability and accuracy. The output waveforms can be both amplitude and frequency modulated by an external voltage. Frequency of operation can be selected externally over a range of 0.01Hz to more than 1MHz.
The circuit is ideally suited for communications, instrumentation, and function generator applications requiring sinusoidal tone, AM, FM, or FSK generation. It has a typical drift specification of 20ppm/°C. The oscillator frequency can be linearly swept over a 2000:1 frequency range with an external control voltage, while maintaining low distortion.

FEATURES
*Low-Sine Wave Distortion, 0.5%, Typical
*Excellent Temperature Stability, 20ppm/°C, Typ.
*Wide Sweep Range, 2000:1, Typical
*Low-Supply Sensitivity, 0.01%V, Typ.
*Linear Amplitude Modulation
*TTL Compatible FSK Controls
*Wide Supply Range, 10V to 26V
*Adjustable Duty Cycle, 1% TO 99%

APPLICATIONS
*Waveform Generation
*Sweep Generation
*AM/FM Generation
*V/F Conversion
*FSK Generation
*Phase-Locked Loops (VCO)

XR-2206P, XR-2206CP, XR-2206D

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GENERAL DESCRIPTION
The AMS222 is a low-cost, oscillator intended to be used as an external clock for low-frequency applications. The device consists of a resistor-programmed oscillator with complementary output stage. An external resistor allows for output frequency range to be adjusted from 10kHz to 6MHz. The complimentary output stage is very useful in paralleling, switching regulators for doubling the output current. AMS222 is offered in SOT-23 5-leads package.

FEATURES
*Low-Cost, Oscillator/Clock Generator
*Simple User Programming
*Output frequency programmable from 10 kHz to 6MHz
*2.7 to 15V Single-Supply Operation
*Output frequency tolerance <1%
*Complementary output signal
*Break before make output signal

APPLICATIONS
*Switch-Mode Power Supplies
*Servers
*Printers
*Embedded Microcontrollers
*Industrial Controls
*Automotive Applications
*Toys

AMS222AM1

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    Tracked from fish finder reviews 2018/08/31 04:49  삭제

    DATASHEETBLOG

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DESCRIPTION
The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as insystem programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

FEATURES
*Three internal PLLs
*Internal non-volatile EEPROM
*JTAG and FAST mode I2C serial interfaces
*Input Frequency Ranges: 1MHz to 400MHz
*Output Frequency Ranges:
-LVTTL: up to 200MHz
-LVPECL/ LVDS: up to 500MHz
*Reference Crystal Input with programmable oscillator gain and programmable linear load capacitance
-Crystal Frequency Range: 8MHz to 50MHz
*Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
*10-bit post-divider blocks
*Fractional Dividers
*Two of the PLLs support Spread Spectrum Generation capability
*I/O Standards:
-Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
-Inputs - 3.3V LVTTL/ LVCMOS
*Programmable Slew Rate Control
*Programmable Loop Bandwidth Settings
*Programmable output inversion to reduce bimodal jitter
*Redundant clock inputs with glitchless auto and manual switchover options
*JTAG Boundary Scan
*Individual output enable/disable
*Power-down mode
*3.3V VDD
*Available in TQFP and VFQFPN packages

IDT5V9888NLGI, IDT5V9888PFGI

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General Description
CY25562 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic interference (EMI) found in today’s high speed digital electronic systems.
CY25562 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is greatly reduced.
This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading system performance.
CY25562 is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Table 1 for programming details.
CY25562 is intended for applications with a reference frequency in the range of 50 to 200 MHz.
A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing.
CY25562 is available in an eight-pin SOIC package with a 0 to 70°C operating temperature range.
Refer to CY25561 for applications with lower drive requirements, and CY25560 with lower drive and frequency requirements.

Features
*50 to 200 MHz Operating Frequency Range
*Wide range of spread selections: 9
*Accepts Clock and Crystal Inputs
*Low Power Dissipation
-70 mW Typ (Fin = 65 MHz)
*Frequency Spread Disable Function
*Center Spread Modulation
*Low Cycle-to-cycle Jitter
*8-pin SOIC Package

Applications
*High resolution VGA controllers
*LCD panels and monitors
*Workstations and servers

CY25562SXC, CY25562SXCT

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Description
This 5 V HCMOS integrated circuit is intended primarily for application in three-phase, sinusoidally commutated brushless motor, induction motor, AC servomotor or UPS PWM modulator control systems. It injects the required deadtime to convert a single phase leg PWM command into the two separate logic signals required to drive the upper and lower semiconductor switches in a PWM inverter. It also provides facilities for output disable and fast overcurrent and fault condition shutdown.
In the IXDP630, deadtime programming is achieved by an internal RC oscillator. In the IXDP631, programming is achieved by use of a crystal oscillator. An alternative for both the IXDP630/631 is with an external clock signal. Because of its flexibility, the IXDP630/631 is easily utilized in a variety of brushed DC, trapezoidally commutated brushless DC, hybrid and variable reluctance step and other more exotic PWM motor drive power and control circuit designs.

Features
*5 V HCMOS logic implementation maintains low power at high speed
*Schmitt trigger inputs and CMOS logic levels improve noise immunity
*Simultaneously injects equal deadtime in up to three output phases
*Replaces 10-12 standard SSI/MSI logic devices
*Allows a wide range of PWM modulation strategies
*Directly drives high speed optocouplers

Applications
*1- and 3- Phase Motion Controls
*1- and 3- Phase UPS Systems
*General Power Conversion Circuits
*Pulse Timing and Waveform Generation
*General Purpose Delay and Filter
*General Purpose Three Channel "One Shot"

IXDP631, IXDP630PI, IXDP631PI

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General Description
CY25561 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic Interference (EMI) found in today’s high speed digital electronic systems.
CY25561 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is reduced.
This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading the system performance.
CY25561 is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Table 2 for programming details.
CY25561 is intended for use with applications with a reference frequency in the range of 50 to 166 MHz.
A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing.
CY25561 is available in an eight-pin SOIC package with a 0°C to 70°C operating temperature range.

Features
*50 to 166 MHz Operating Frequency Range
*Wide Range of Spread Selections:9
*Accepts Clock and Crystal Inputs
*Low Power Dissipation
-70 mW–Typ at 66 MHz
*Frequency Spread Disable Function
*Center Spread Modulation
*Low Cycle-to-cycle Jitter
*8-pin SOIC Package

Applications
*Desktop, notebook, and tablet PCs
*VGA controllers
*LCD panels and monitors
*Workstations and servers

CY25561SXC, CY25561SXCT

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DESCRIPTION
MB88154 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency.

FEATURE
*Input frequency : 16.6 MHz to 67 MHz
*Output frequency: 16.6 MHz to 67 MHz (One time input frequency)
*Modulation rate can select from ± 0.5%, ± 1.0%, ± 1.5% or − 1.0%, − 2.0%, − 3.0%. (For center spread / down spread.)
*Equipped with crystal oscillation circuit: Range of oscillation 16.6 M MHz to 48 MHz
*The external clock can be input: 16.6 MHz to 67 MHz
*Modulation clock output Duty : 40% to 60%
*Modulation clock Cycle-Cycle Jitter : Less than 100 ps
*Low current consumption by CMOS process : 5.0 mA (24 MHz : Typ-sample, no load)
*Power supply voltage : 3.3 V ± 0.3 V
*Operating temperature : − 40 °C to +85 °C
*Package : SOP 8-pin

MB88154-102, MB88154-103, MB88154-112, MB88154-113

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Description
Lattice’s Power Manager II ispPAC-POWR1014/A is general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS® technology. The
ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor up to 10 power supply test points. Each of these input channels has two independently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-compare)
monitor functions. Four general-purpose digital inputs are also provided for miscellaneous control functions.
The ispPAC-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Two of these outputs HVOUT1-HVOUT2) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can provide up to 10V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.
The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32μs to 2 seconds. The CPLD is programmed using Logi-Builder™, an easy-to-learn language integrated into the PAC-Designer® software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the VMON voltage through the I2C bus of the ispPACPOWR1014A device.
The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN4 and control the output pins (ispPAC-POWR1014A only).

Features
*Monitor and Control Multiple Power Supplies
- Simultaneously monitors up to 10 power supplies
- Provides up to 14 output control signals
- Programmable digital and analog circuitry
*Embedded PLD for Sequence Control
- 24-macrocell CPLD implements both state machines and combinatorial logic functions
*Embedded Programmable Timers
- Four independent timers
- 32μs to 2 second intervals for timing sequences
*Analog Input Monitoring
- 10 independent analog monitor inputs
- Two programmable threshold comparators per analog input
- Hardware window comparison
- 10-bit ADC for I2C monitoring (ispPACPOWR1014A only)
*High-Voltage FET Drivers
- Power supply ramp up/down control
- Programmable current and voltage output
- Independently configurable for FET control or digital output
*2-Wire (I2C/SMBus™ Compatible) Interface
- Comparator status monitor
- ADC readout
- Direct control of inputs and outputs
- Power sequence control
- Only available with ispPAC-POWR1014A
*3.3V Operation, Wide Supply Range 2.8V to 3.96V
- In-system programmable through JTAG
- Industrial temperature range: -40°C to +85°C
- 48-pin TQFP package, lead-free option

ispPAC-POWR1014A-01T48I, ispPAC-POWR1014-01T48I,
ispPAC-POWR1014A-01TN48I, ispPAC-POWR1014-01TN48I

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DESCRIPTION
The WM8951L is a low power stereo ADC with an integrated microphone interface and crystal oscillator for clock generation. The WM8951L is ideal for voice recorders, wireless microphones and games console accessories.
Stereo line and mono microphone level audio inputs are provided, along with a mute function, programmable line level volume control and a bias voltage output suitable for an electret type microphone.
Stereo 24-bit multi-bit sigma delta ADCs are used with oversampling decimation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported.
The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including volume controls, mutes and extensive power management facilities. The device is available in a small 28 lead 5x5mm quad flat leadless package (QFN).

FEATURES
*Audio Performance
- ADC SNR 90dB (‘A’ weighted) at 3.3V, 85dB at 1.8V
- Low Power
- 1.42 – 3.6V Digital Supply Operation
- 1.8 – 3.6V Analogue Supply Operation
*Sampling Frequency: 8kHz – 96kHz
*Selectable ADC High Pass Filter
*2 or 3-Wire MPU Serial Control Interface
*Programmable Audio Data Interface Modes
- I2S, Left, Right Justified or DSP
- 16/20/24/32 bit Word Lengths
- Master or Slave Clocking Mode
*Microphone Input and Electret Bias with Side Tone Mixer
*Available in 5x5mm 28-lead QFN package

APPLICATIONS
*Wireless microphones
*Voice recorders
*Games console accessories

WM8951LGEFL, WM8951LGEFL/R

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