Description
 The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package.
Output is disabled when the associated output enable (OE) input is low.
To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current souring capability of the driver.
Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.

Features
* The basic gate function is lined up as hitachi uni logic series.
* Supplied on emboss taping for high speed automatic mounting.
* TTL compatible input level.
- Supply voltage range : 4.5 to 5.5 V
- Operating temperature range : –40 to +85°C
* All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
- All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
* Output current ±12 mA (@VCC = 4.5 V to 5.5 V)
* All the logical input has hysteresis voltage for the slow transition.

TAG Buffer, Gate

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Description
The CPC1580 optical gate driver provides isolated control of a discrete power MOSFET transistor without the need of an external power supply.
Control of the power MOSFET transistor is accomplished by the application of sufficient input LED current to activate the driver circuitry.
On the load side, an external storage capacitor and an internal bootstrap diode enable the internal photovoltaic and gate driver circuitry to provide fast output switching characteristics by supplying the charge necessary to satisfy the MOSFET’s bias requirements.
Provided in a small 8-pin package, the CPC1580 provides 3750Vrms of input-to-output isolation.

Features
• Drives External Power MOSFET
• Low LED Current (2.5mA)
• Requires No External Power Supply
• Load Voltages up to 65V
• High Reliability
• Small 8-pin Surface Mount Package
• 3750Vrms Input/Output Isolation

Applications
• Industrial Controls
• Instrumentation
• Medical Equipment Isolation
• Electronic Switching
• I/O Subsystems
• Appliances

CPC1580P
CPC1580PTR

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General description
The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

Features
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
* JESD8-12 (0.8 V to 1.3 V)
* JESD8-11 (0.9 V to 1.65 V)
+ JESD8-7 (1.2 V to 1.95 V)
+ JESD8-5 (1.8 V to 2.7 V)
+ JESD8-B (2.7 V to 3.6 V)
* ESD protection:
+ HBM JESD22-A114E Class 3A exceeds 5000 V
+ MM JESD22-A115-A exceeds 200 V
+ CDM JESD22-C101-C exceeds 1000 V
* Low static power consumption; ICC = 0.9 mA (maximum)
* Latch-up performance exceeds 100 mA per JESD 78 Class II
* Inputs accept voltages up to 3.6 V
* Low noise overshoot and undershoot < 10 % of VCC
* IOFF circuitry provides partial Power-down mode operation
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G386GW
74AUP1G386GM
74AUP1G386GF

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General description
The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G00 provides the single 2-input NAND function.

Features
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
 + JESD8-12 (0.8 V to 1.3 V)
 + JESD8-11 (0.9 V to 1.65 V)
 + JESD8-7 (1.2 V to 1.95 V)
 + JESD8-5 (1.8 V to 2.7 V)
 + JESD8-B (2.7 V to 3.6 V)
* ESD protection:
 + HBM JESD22-A114-C Class 3A. Exceeds 5000 V
 + MM JESD22-A115-A exceeds 200 V
 + CDM JESD22-C101-C exceeds 1000 V
* Low static power consumption; ICC = 0.9 mA (maximum)
* Latch-up performance exceeds 100 mA per JESD 78 Class II
* Inputs accept voltages up to 3.6 V
* Low noise overshoot and undershoot < 10 % of VCC
* IOFF circuitry provides partial Power-down mode operation
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G00GW
74AUP1G00GM
74AUP1G00GF

TAG Gate, NAND

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Features
• UltraFast switching speed optimized for operating frequencies 8 to 40kHz in hard switching, 200kHz in resonant mode soft switching
• Generation 4 IGBT design provides tighter parameter distribution and higher efficiency (minimum switching and conduction losses) than prior generations
• Industry-benchmark Super-247 package with higher power handling capability compared to same footprint TO-247
• Creepage distance increased to 5.35mm
• Lead-Free

Benefits
• Generation 4 IGBT's offer highest efficiencies available
• Maximum power density, twice the power handling of the TO-247, less space than TO-264
• IGBTs optimized for specific application conditions
• Cost and space saving in designs that require multiple, paralleled IGBTs
• HEXFREDTM antiparallel Diode minimizes switching losses and EMI

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Features
■ Very high speed-10 MBit/s
■ Superior CMR-10 kV/µs
■ Double working voltage-480V
■ Fan-out of 8 over -40°C to +85°C
■ Logic gate output
■ Strobable output
■ Wired OR-open collector
■ U.L. recognized (File # E90700)

Applications
■ Ground loop elimination
■ LSTTL to TTL, LSTTL or 5-volt CMOS
■ Line receiver, data transmission
■ Data multiplexing
■ Switching power supplies
■ Pulse transformer replacement
■ Computer-peripheral interface

Description
 The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/ 2631 dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13mA (fan out of 8).
 An internal noise shield provides superior common mode rejection of typically 10kV/µs. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/µs. The HCPL-2611 has a minimum
CMR of 10 kV/µs.

HCPL-2601
HCPL-2611
HCPL-2630
HCPL-2631

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TA8316AS is a dedicated IC integrating IGBT gate drive circuits on a single chip.
A high current directly drives IGBT.

FEATURES
* Can directly control from a microcontroller
* Can directly drive the IGBT gate using a high current.
   Source current : -200mA(max), sink current 1A(max)
* Incorporates a diode to protect the IGBT gate at power on.
TAG Driver, Gate, IGBT

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General Description
The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

* Typical propagation delay: 8 ns
* Wide power supply range: 2–6V
* Low quiescent current: 20 mA maximum (74HC Series)
* Low input current: 1 ㎂ maximum
* Fanout of 10 LS-TTL loads

MM74HC00M MM74HC00SJ MM74HC00MTC MM74HC00N MTC14
TAG Gate, NAND, Quad

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* HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V
* LOW POWER DISSIPATION: ICC = 2 mA (MAX.) at TA=25°C
* HIGH NOISE IMMUNITY: VNIH =VNIL = 28% VCC (MIN.)
* POWER DOWNPROTECTION ON INPUTS
* SYMMETRICAL OUTPUT IMPEDANCE: lIOH| = IOL = 8mA (MIN)
* BALANCED PROPAGATION DELAYS: tPLH = tPHL
* OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V
* PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 00
* IMPROVED LATCH-UP IMMUNITY
* LOW NOISE: VOLP = 0.8V (MAX.)

DESCRIPTION
The 74VHC00 is an advanced high-speed CMOS QUAD 2-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal wiring C2MOS technology.
The internal circuit is composed of 3 stages including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and outputs are equipped with protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess voltage.

74VHC00M 74VHC00MTR 74VHC00TTR
TAG Gate, Input, Quad

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DESCRIPTION
The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8).
An internal noise shield provides superior common mode rejection of typically 10 kV/µs. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/µs. The HCPL-2611 has a minimum CMR of 10 kV/µs.

FEATURES
• Very high speed-10 MBit/s
• Superior CMR-10 kV/µs
• Double working voltage-480V
• Fan-out of 8 over -40°C to +85°C
• Logic gate output
• Strobable output
• Wired OR-open collector
• U.L. recognized (File # E90700)

HCPL-2601 HCPL-2631 HCPL-2611 HCPL-2630

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