1. GSPS internal clock speed (up to 400 MHz out directly)
- Integrated 1 GSPS 14-bit DAC
- 48-bit frequency tuning word
- Differential HSTL Comparator
- Flexible System Clock Input accepts either crystal or external reference clock.
- On-chip Low-Noise PLL REFCLK Multiplier
2. Spur Reduction Channels
- Low Jitter clock doubler for frequencies up to 750 MHz
- Single-ended CMOS Comparator; frequencies < 50MHz
- Programmable output divider for CMOS output
- Serial I/O control
- Excellent Dynamic Performance
- Software controlled power-down
- 64-lead LFCSP package
- Phase Noise @ 95MHz using Vectron VCC6 87.5MHz Oscillator:
100 Hz Offset: -103 dBc/Hz
10 kHz Offset: -133 dBc/Hz
1 MHz Offset: -136 dBc/Hz

- Agile LO frequency synthesis
- Low jitter, fine tune clock generation
- Test and measurement equipment
- Wireless Base Stations, Controllers
- Secure Communications
- Fast frequency hopping

 The AD9912 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC. The AD9912 features a 48–bit frequency tuning word (FTW) which can synthesize frequencies in step sizes no larger than 4 uHz. Absolute frequency accuracy can be achieved by adjusting the DAC
system clock.
 The AD9912 also features an integrated system clock PLL, which allows reference clocks as low as 25 MHz. The AD9912 operates over an industrial temperature range, spanning -40°C to +85°C.

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General Description
 The ADC08D1500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range.

 The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.25 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

 Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sample rate. The two converters can be interleaved and
used as a single 3 GSPS ADC. The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ Interleave Mode for 2x Sample Rate
■ Multiple ADC Synchronization Capability
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Fine Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock

Key Specifications
■ Resolution 8 Bits
■ Max Conversion Rate 1.5 GSPS (min)
■ Bit Error Rate 10-18 (typ)
■ ENOB @ 748 MHz Input 7.25 Bits (typ)
■ DNL ±0.15 LSB (typ)
■ Power Consumption
■ — Operating 1.8 W (typ)
— Power Down Mode 3.5 mW (typ)

■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation

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