Description
 The HD61203U is a common signal driver for dot matrix liquid crystal graphic display systems.
It generates the timing signals (switch signal to convert LCD waveform to AC, frame synchronous signal) and supplies them to the column driver to control display.
It provides 64 driver output lines and the impedance is low enough to drive a large screen.
As the HD61203U is produced by a CMOS process, it is fit for use in portable battery-driven equipment utilizing the liquid crystal display’s low power consumption.
The user can easily construct a dot matrix liquid crystal graphic display system by combining the HD61203U and the column (segment) driver HD61202U.

Features
* Dot matrix liquid crystal graphic display common driver with low impedance
* Low impedance: 1.5 kW max
* Internal liquid crystal display driver circuit: 64 circuits
* Internal dynamic display timing generator circuit
* Display duty cycle
* When used with the column driver HD61202U: 1/48, 1/64, 1/96, 1/128
* When used with the controller HD61830: Selectable out of 1/32 to 1/128
* Low power dissipation: During displays: 5 mW
* Power supplies: VCC: 2.7~5.5V
* Power supply voltage for liquid crystal display drive: 8V to 16V
* CMOS process
* 100-pin plastic QFP, 100-pin plastic TQFP, chip

HD61203UFS
HD61203UTE
HCD61203U

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FEATURES
· Analog Channels
– –6-dB to 6-dB Analog Gain
– Analog Input Multiplexers (MUXs)
– Automatic Video Clamp
– Three Digitizing Channels, Each With Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC)
– Clamping: Selectable Clamping Between Bottom Level and Mid-Level
– Offset: 1024-Step Programmable RGB or YPbPr Offset Control
– Gain: 8-Bit Programmable Gain Control
– ADC: 8-/10-Bit 165-/110-MSPS ADC
– Automatic Level Control (ALC) Circuit
– Composite Sync: Integrated Sync-on-Green Extraction From Green/Luminance Channel
– Support for DC- and AC-Coupled Input Signals
– Supports Component Video Standards 480i, 576i, 480p, 576p, 720p, 1080i, and 1080p
– Supports PC Graphics Inputs up to UXGA
– Programmable RGB-to-YCbCr Color Space Conversion
· Horizontal PLL
– Fully Integrated Horizontal PLL for Pixel Clock Generation
– 12-MHz to 165-MHz Pixel Clock Generation From HSYNC Input
– Adjustable Horizontal PLL Loop Bandwidth for Minimum Jitter
– 5-Bit Programmable Subpixel Accurate Positioning of Sampling Phase
· Output Formatter
– Supports 20-bit 4:2:2 Outputs With Embedded Syncs
– Support for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board Traces
– Dedicated DATACLK Output With Programmable Output Polarity for Easy Latching of Output Data
· System
– Industry-Standard Normal/Fast I2C Interface With Register Readback Capability
– Space-Saving 100-Pin TQFP Package
– Thermally-Enhanced PowerPAD™ Package for Better Heat Dissipation
– Glueless Interface to TVP9000/9001 Video Processor Back-End Devices

APPLICATIONS
· LCD TV/Monitors/Projectors
· DLP TV/Projectors
· PDP TV/Monitors
· LCOS TV/Monitors
· PCTV Set-Top Boxes
· Digital Image Processing
· Video Capture/Video Editing
· Scan Rate/Image Resolution Converters
· Video Conferencing
· Video/Graphics Digitizing Equipment

DESCRIPTION
 TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 ´ 1200) resolution at 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p.

 The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.

 TVP7002 also contains a complete horizontal PLL block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.
All programming of the part is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.

TVP7002PZP
TVP7002PZPR

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