The PI90SD1636C is a single chip, Gigabit Ethernet transceiver. It performs all the functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specifi ed by the IEEE
802.3z Gigabit Ethernet standard. These functions include parallelto-serial and serial-to-parallel conversion, clock gen er a tion, clock data re cov ery, and word synchronization. In addition, an internal loopback function is provided for system debugging.
The PI90SD1636C is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point applications. The device supports 1000BASE-LX and 1000BASE-SX fi ber-optic media, and 1000BASE-CX copper media.
The transmitter section of the PI90SD1636C accepts 10-bit wide parallel TTL data and converts it to a high speed serial data stream. The parallel data is encoded in 8b/10b format. This incoming parallel data is latched into an input register, and synchronized on the rising edge of the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125 MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used to provide the high speed serial data output. The output is sent through a Pseudo Emitter Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of 1000BASE-CX medium, or to a fi ber optic module in the case of 1000BASE-LX or 1000BASE SX fi ber optic medium.
The receiver section of the PI90SD1636C accepts a serial PECLcom pat i ble data stream at a 1.25 Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A PLL locks onto the incoming serial data stream, and recovers the 1.25 GHz high speed serial clock and data. This is accomplished by contin u al ly frequency locking onto the 125 MHz reference clock, and by phase locking onto the incoming data stream. The serial data is converted back to parallel data format. The ‘comma’ character is used to establish byte alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are alternately used to clock out the parallel data on the rising edge. This parallel data is sent to the user in TTL-compatible form.

* IEEE 802.3z Gigabit Ethernet Compliant
*Supports 1.25 Gbps Using NRZ Coding over uncompensated twin coax cable
*Fully integrated CMOS IC
*Low Power Consumption
*ESD rating >2000V (Human Body Model) or > 200V (Machine Model)
*5-Volt Input Tolerance
*Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A and Vitesse VSC7123 transceivers (see Appendix A)
*Packaging (Pb-free & Green available):
-64-pin LQFP (FC)
-64-pin LQFP (FD)

*Gigabit Ethernet
*Serial Backplane
*Proprietary point-to-point applicaitons
*Passive Optical Networks

PI90SD1636CFC, PI90SD1636CFCE, PI90SD1636CFD, PI90SD1636CFDE

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The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber optic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a lowspeed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW.
The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip.

*Operating rate
*1250 MHz (Gigabit Ethernet) line rates
*Half and full VCO output rates
*Functionally compliant IEEE 802.3z Gigabit Ethernet standard
*Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference
*Receiver PLL provides clock and data recovery
*10-bit parallel TTL compatible interface
*Low-jitter serial LVPECL compatible interface
*Local loopback
*Single +3.3 V supply, 620 mW power dissipation
*64 PQFP or TQFP package
*Continuous downstream clocking from receiver
*Drives 30 m of Twinax cable directly

*Frame buffer
*Switched networks
*Data broadcast environments
*Proprietary extended backplanes

S2060A, S2060B, S2060C, S2060D

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The Am79761 Gigabit Ethernet Physical Layer Serializer/Deserializer (GigaPHY-SD) device is a 1.25 Gbps Ethernet Transceiver optimized for Gigabit Ethernet/1000BASE-X applications. It implements the Physical Medium Attachment (PMA) layer for a single port.
The GigaPHY-SD device can interface to fiber-optic media to support 1000BASE-LX and 1000BASE-SX applications and can interface to copper coax to support 1000BASE-CX applications.
The functions performed by the device include serializing the 8B/10B 10-bit data for transmission, deserializing received code groups, recovering the clock from the incoming data stream, and word synchronization.
When transmitting, the GigaPHY-SD device receives 10-bit 8B/10B code groups at 125 million code groups per second. It then serializes the parallel data stream, adding a reference clock, and transmits it through the PECL drivers.
When receiving, the GigaPHY-SD device receives the PECL data stream from the network. It then recovers the clock from the data stream, deserializes the data stream into a 10-bit code group, and transmits it to the Physical Coding Sublayer (PCS) logic above. Optionally, it detects comma characters used to align the incoming word.

*Gigabit Ethernet Transceiver operates at 1.25 Gigabits per second (Gbps)
*Suitable for both Coaxial and Optical Link applications
*10-bit TTL Interface for Transmit and Receive Data
*Monolithic Clock Synthesis and Clock Recovery requires no external components
*Word Synchronization Function (Comma Detect)
*Low Power Operation - 700 mW typical
*64-pin Standard PQFP
-14 x 14 mm (0° C - 70° C)
-10 x 10 mm (0° C - 50° C)
*125 MHz TTL Reference Clock
*Loopback Diagnostic
*Single +3.3 V Supply

AM79761YC-10, AM79761YC-14

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• Fifth generation of StrataSwitch® and StrataXGS® product line
• 24 10/100/1000 Mbps Ethernet ports supporting SGMII and SerDes interfaces for both copper and fiber connections
• The BCM56510 device, is a powerful, highly-integrated member of the scalable StrataXGS III product family
• Line-rate switching for all packet sizes and conditions
• On-chip data packet memory and table memory
• IPv6 routing and tunneling
• Advanced ContentAware™ classification Filtering Processors (FP)
• Advanced security features in hardware
• Port-trunking and mirroring supported across stack
• Advanced packet flow control:
• Head-of-line blocking prevention
• Back pressure support
• Eight QoS queues per port with hierarchical minimum/ maximum shaping per Classes of Service (CoS) per queue per port
• Standard compliant 802.1ad provider bridging

• Highly scalable BroadScale™ architecture evolved from five generations of switching experience provides rich features, scalability, and future proof solutions.
• Optimized for secure switching and convergence of wired and wireless applications and services in networks
• System vendors can build scalable high-performance, high-port density GbE LAN switches in several form factors.
• Multiple CoS and low latency enable the support of VoIP and triple play services.
• Built-in high-speed serial interfaces with Broadcom-unique SerDes technology ease and accelerate system design, while reducing cost and conserving board space.
• Broadcom switch API compatibility enables software reuse and faster time-to-market.
• Small package and low power enables cost-effective and highperformance system design.

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