'GDDR' related articles 1

  1. 2009/12/12 HY5DU283222Q - 128M(4Mx32) GDDR SDRAM
The Hynix HY5DU283222Q is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

*VDD, VDDQ = 2.5V ± 5%
*All inputs and outputs are compatible with SSTL_2 interface
*JEDEC standard 20mm x 14mm 100pin LQFP with 0.65mm pin pitch
*Fully differential clock inputs (CK, /CK) operation
*Double data rate interface
*Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
*Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
*Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe
*All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock
*Write mask byte controls by DM (DM0 ~ DM3)
*Programmable /CAS Latency 3 and 4 supported
*Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
*Internal 4 bank operations with single pulsed /RAS
*tRAS Lock-Out function supported
*Auto refresh and self refresh supported
*4096 refresh cycles / 32ms
*Half strength and Matched Impedance driver option controlled by EMRS

HY5DU283222Q-4, HY5DU283222Q-45, HY5DU283222Q-5, HY5DU283222Q-55

Trackback :: http://datasheetblog.com/trackback/2920

댓글을 달아 주세요 Comment