* Operating Range 2-V to 5.5-V VCC
* Contain Six Flip-Flops With Single-Rail Outputs
* Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
* Latch-Up Performance Exceeds 250 mA Per JESD 17
* ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

description
The ’AHC174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are designed for 2-V to 5.5-V VCC operation.
Information at the data (D) inputs that meets the setup time requirements is transferred to the
outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

SN74AHC174N
SN74AHC174D
SN74AHC174DR
SN74AHC174NSR
SN74AHC174DBR

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* HIGH SPEED: fMAX = 90MHz (TYP.) at VCC = 6V
* LOW POWER DISSIPATION: ICC = 4μA(MAX.) at TA=25°C
* HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
* SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)
* BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
* WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V
* PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 374
* SPACE GRADE-1: ESA SCC QUALIFIED
* 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST
* NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION
* DEVICE FULLY COMPLIANT WITH SCC-9203-060

DESCRIPTION
The M54HC374 is an high speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
NON INVERTING fabricated with sub-micron silicon gate C2MOS technology.
This 8 bit D-TYPE FLIP FLOP is controlled by a clock input (CK) and an output enable input (OE).

On the positive transition of the clock, the Q outputs will be set to the logic state that were
setup at the D inputs.
While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is high the outputs will be in a high impedance state.
The output control does not affect the internal operation of flip-flops; that is, the old data can be
retained or the new data can be entered even while the outputs are off.
All inputs are equipped with protection circuits against static discharge and transient excess
voltage.

M54HC374D
M54HC374K
M54HC374D1
M54HC374K1

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FEATURES
• Metastable immune characteristics
• Pin compatible with 74F74 and 74F5074
• Typical fMAX = 200 MHz
• Output skew guaranteed less than 2.0 ns
• High source current (IOH = 15 mA) ideal for clock driver applications
• Output capability: +20 mA / –15 mA
• Latch-up protection exceeds 50 0mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set and reset inputs; also true and complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active-LOW inputs and operate independently of the clock (CPn) input. Data must be stable just one set-up time prior to the LOW-to-HIGH transition of the clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output.
The 74ABT5074 is designed so that the outputs can never display a metastable state due to set-up and hold time violations. If set-up time and hold time are violated the propagation delays may be extended beyond the specifications, but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74ABT5074 are:

t @ 94 ps and To @ 1.3 × 107 sec
where t represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.


74ABT5074D
74ABT5074DB
74ABT5074PW

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Features
■ High speed: fMAX=140MHz (Typ.) at TA=25°C
■ High noise immunity: VIH=2.0V, VIL=0.8V
■ Power down protection is provided on all inputs andoutputs
■ Low power dissipation: ICC=4µA (Max.) @ TA=25°C
■ Pin and function compatible with 74HCT374

General Description
 The VHCT374A is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state.

 Protection circuits ensure that 0V to 7V can be applied to the input and output
(1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V
systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Note:
1. Outputs in OFF-State.

74VHCT374AM
74VHCT374ASJ
74VHCT374AMTC

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Features
■ High Speed: tPD=5.4ns (typ) at VCC=5V
■ High noise immunity: VNIH=VNIL=28% VCC(Min.)
■ Power down protection is provided on all inputs
■ Low power dissipation: ICC=4µA (Max) @ TA=25°C
■ Pin and function compatible with 74HC374

General Description
 The VHC374 is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a HIGH impedance state.

 An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched
supply and input voltages.

74VHC374M
74VHC374SJ
74VHC374MTC

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Features
• Ideal Buffer for MOS Microprocessor or Memory
• Eight Edge-Triggered D Flip−Flops
• Buffered Common Clock
• Buffered, Asynchronous Master Reset
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• Outputs Source/Sink 24 mA
• ACT273 Has TTL Compatible Inputs
• Pb−Free Packages are Available*

MC74AC273N MC74AC273NG MC74ACT273N MC74ACT273NG MC74AC273DW MC74AC273DWG
MC74AC273DWR2 MC74AC273DWR2G MC74AC273DTR2 MC74AC273DTR2G MC74ACT273DW
MC74ACT273DWG MC74ACT273DWR2 MC74ACT273DWR2G MC74ACT273DTR2
MC74ACT273DTR2G MC74AC273MEL MC74AC273MELG MC74ACT273M MC74ACT273MG
MC74ACT273MEL MC74ACT273MELG

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FEATURES
* Output capability: standard
* ICC category: flip-flops

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
 The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
 The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
 The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

74HCT107

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 The MC14013B dual type D flip–flop is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each flip–flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip–flops for counter and toggle applications.
• Static Operation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse
• Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4013B

MC14013BCP MC14013BD MC14013BDR2 MC14013BDT
TAG Flip-Flop

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General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Features
  - Alternate military/aerospace device (54LS74) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.

54LS74DMQB, 54LS74FMQB, 54LS74LMQB, DM54LS74AJ, DM54LS74AW, DM74LS74AM, DM74LS74AN
TAG Flip-Flop

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GENERAL DESCRIPTION
The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state.Operation of the OE input does not affect the state of the flip-flops.
The “574” is functionally identical to the “564”, but has non-inverting outputs.
The “574” is functionally identical to the “374”, but has a different pinning.

FEATURES
· 3-state non-inverting outputs for bus oriented applications
· 8-bit positive edge-triggered register
· Common 3-state output enable input
· Independent register and 3-state buffer operation
· Output capability: bus driver
· ICC category: MSI

74HC574D, 74HC574N, 74HC574DB, 74HCT574D, 74HCT574N, 74HCT574DB

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