General Description
The AAT2848 is a tri-mode charge pump optimized for systems operating with lithium-ion/polymer batteries. The charge pump provides power for both white LED backlight and flash, with an integrated four channel backlight LED current sink plus two channel flash LED current sinks.
Each backlight channel can drive up to 30mA, while each flash current sink/channel can drive up to 300mA (600mA total). Two independent S2Cwire™ (AnalogicTech’s Simple Serial Control™) serial digital interface inputs enable, disable, and set LED current to one of 32 levels for the backlight and to one of 16 levels for the flash, with fullscale current independently set for backlight and flash using external resistors.
The AAT2848 offers a built-in fade-in/out function for linear control of the backlight current during ON/OFF transitions. The fade time is programmable by an external capacitor.
The AAT2848 also offers a built-in flash timeout function as a safety feature associated with the high power flash driver. The safety timer is also programmable via an external capacitor.
The AAT2848 is equipped with built-in short-circuit and over-temperature protection. The soft-start circuitry prevents excessive inrush current at start-up and mode transitions. The AAT2848 is available in a Pb-free, space saving TQFN33-20 package and operates over the -40°C to +85°C ambient temperature range.

Features
*Tri-Mode (1x/1.5x/2x) Charge Pump
*Four 30mA Backlight LED Channels
*Independent S2Cwire Control for Backlight
*32-Level Programmable Backlight Current Control—Linear, Inverting
*Two 300mA Flash LED Channels
*Independent S2Cwire Control for Flash
*16-Level Programmable Flash Current Control—Linear, Inverting
*User-Programmable Full Scale Current for Backlight and Flash
*User-Programmable Fade-In/Fade-Out Function for Backlight
*User-Programmable Safety Timer for Flash LED Protection
*Built-In Thermal Protection
*Automatic Soft-Start
*-40°C to +85°C Temperature Range
*Available in TQFN33-20 Package

Applications
*Camera Enabled Mobile Devices
*Digital Still Cameras
*Multimedia Mobile Phones

AAT2848IDG-T1
TAG Display, Flash

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Description
The M25P10-A is a 1 Mbit (128 Kbit x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

Features
*1 Mbit of Flash memory
*Page Program (up to 256 bytes) in 1.4 ms (typical)
*Sector Erase (256 Kbit) in 0.65 s (typical)
*Bulk Erase (1 Mbit) in 1.7 s (typical)
*2.3 to 3.6 V single supply voltage
*SPI bus compatible serial interface
*50 MHz Clock rate (maximum)
*Deep Power-down mode 1 μA (typical)
*Electronic signatures
–JEDEC standard two-byte signature (2011h)
–RES instruction, one-byte signature (10h), for backward compatibility
*More than 20 years’ data retention
*Packages
–ECOPACK® (RoHS compliant)

M25P10-AVMN6TP/X, M25P10-AVMP6TP/X, M25P10-AVMB6TP/X

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Description
The CXA1396D are 8-bit ultrahigh-speed flash A/D converter ICs capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of these A/D converters are compatible with the ECL 100K/10KH/10K.
The CXA1396D is pin-compatible with the earlier model CX20116. They can replace the earlier models respectively, without any design changes, in most cases. Compared with the earlier models, these new models have been greatly improved in performance, by incorporating advanced process, new circuit design and carefully considered layout.

Features
*Ultrahigh-speed operation with maximum conversion rate of 125 MSPS (Min.)
*Wide analog input bandwidth: 200MHz (Min. for full-scale input)
*Low power consumption: 870mW (Typ.)
*Single power supply: –5.2V
*Low input capacitance
*Built-in integral linearity compensation circuit
*Low error rate
*Operable at 50% clock duty cycle
*Good temperature charactcristics
*Capable of driving 50½ loads

Applications
*Digital oscilloscopes
*HDTV (high-definition TVs)
*Other apparatus requiring ultrahigh-speed A/D conversion

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General Description
The AAT2806 is a dual charge pump designed to support both the white LED backlight and flash applications for systems operating with lithium-ion/polymer batteries. The backlight charge pump is capable of driving up to four LEDs at a total of 80mA. The current sinks may be operated individually or in parallel for driving higher current LEDs. To maximize power efficiency, the charge pump operates in 1X, 1.5X, or 2X mode, where the mode of operation is automatically selected by comparing the forward voltage of each LED with the input voltage. AnalogicTech's S2Cwire™ (Simple Serial Control™) serial digital input is used to enable, disable, and set current for each LED with an eight-level logarithmic scale plus four low-current settings down to 50μA for optimized efficiency, with a typical operating quiescent current of less than 50μA.
The flash charge pump is a charge pump doubler with a regulated output voltage. It is designed to deliver 120mA of continuous current and up to 250mA of pulsed current. It has an independent
enable pin for improved power savings.
The AAT2806 has thermal protection and built-in softstart circuitry. A low-current shutdown feature disconnects the load from VIN and reduces quiescent current to less than 1μA.
The AAT2806 is available in a Pb-free, space-saving, thermally-enhanced TDFN44-16 package and is rated over the -40°C to +85°C temperature range.

Features
*VIN Range: 2.7V to 5.5V
*Dual Charge Pump to Support Backlight and Flash LEDs
*Backlight Charge Pump:
-Regulated Current
-Four Current Sink Inputs
-S2Cwire Brightness Control
-Tri-Mode Charge Pump
-Maximum 20mA of Current Per Input
-Low IQ (50μA) in Light Load Mode
*Flash Charge Pump:
-Regulated Output Voltage
-Up to 250mA of Pulsed Current
*Independent Backlight/Flash Control
*Low Noise 1MHz Constant Frequency Operation
*Automatic Soft Start
*No Inductors
*Available in TDFN44-16 Package

Applications
*Color (RGB) Lighting
*White LED Backlighting
*White LED Photo Flash

AAT2806IXN-4.5-T1

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PRODUCT DESCRIPTION
The SST39WF400A device is a 256K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF400A writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories.
Featuring high-performance Word-Program, the SST39WF400A device provides a typical Word-Program time of 28 μsec. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent writes, it has on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39WF400A device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, it significantly improves performance and reliability, while lowering power consumption. It inherently uses less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39WF400A is offered in both a 48-ball TFBGA package and 48-ball Micro-Packages. See Figures 1 and 2 for pin assignments.

FEATURES
*Organized as 256K x16
*Single Voltage Read and Write Operations
– 1.65-1.95V
*Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
*Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 1 μA (typical)
*Sector-Erase Capability
– Uniform 2 KWord sectors
*Block-Erase Capability
– Uniform 32 KWord blocks
*Fast Read Access Time
– 90 ns
– 100 ns
*Latched Address and Data
*Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 μs (typical)
*Automatic Write Timing
– Internal VPP Generation
*End-of-Write Detection
– Toggle Bit
– Data# Polling
*CMOS I/O Compatibility
*JEDEC Standard
– Flash EEPROM Pinouts and command sets
*Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm) Micro-Package
– 48-bump XFLGA (4mm x 6mm) Micro-Package

SST39WF400A-90-4C-B3K, SST39WF400A-90-4C-B3KE

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General Description
The S29NS128J, S29NS064J, S29NS032J and S29NS016J are 128 Mbit, 64 Mbit, 32 Mbit and 16 Mbit 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 8,388,608, 4,194,304, 2,097,152 and 1,048,576. words of 16 bits each. These devices use a single VCC of 1.7 to 1.95 V to read, program, and erase the memory array. A 12.0-volt Acc may be used for faster program performance if desired. These devices can also be programmed in standard EPROM programmers.

Features
*Single 1.8 volt read, program and erase (1.7 to 1.95 V)
*Multiplexed Data and Address for reduced I/O count
– A15–A0 multiplexed as DQ15–DQ0
– Addresses are latched by AVD# control input when CE# low
*Simultaneous Read/Write operation
– Data can be continuously read from one bank while executing erase/program functions in other bank
– Zero latency between read and write operations
*Read access times at 54 MHz (CL=30 pF)
– Burst access times of 11/13.5 ns at industrial temperature range
– Asynchronous random access times of 65/70 ns
– Synchronous random access times of 71/87.5 ns
*Burst Modes
– Continuous linear burst
– 8/16/32 word linear burst with wrap around
– 8/16/32 word linear burst without wrap around
*Power dissipation (typical values, 8 bits switching, CL = 30 pF)
– Burst Mode Read: 25 mA
– Simultaneous Operation: 40 mA
– Program/Erase: 15 mA
– Standby mode: 9 μA
*Sector Architecture
– Four 8 Kword sectors
– Two hundred fifty-five (S29NS128J), one hundred twenty-seven (S29NS064J),sixty-three (S29NS032J), or thirty-one (S29NS016J) 32 Kword sectors
– Four banks (see next page for sector count and size)
*Sector Protection
– Software command sector locking
– WP# protects the two highest sectors
– All sectors locked when Acc = VIL
*Handshaking feature
– Provides host system with minimum possible latency by monitoring RDY
*Supports Common Flash Memory Interface (CFI)
*Software command set compatible with JEDEC 42.4 standards
– Backwards compatible with Am29F and Am29LV families
*Manufactured on 110 nm process technology
*Embedded Algorithms
– Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically writes and verifies data at specified addresses
*Data# Polling
– Provides a software method of detecting program and erase operation completion
*Erase Suspend/Resume
– Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
*Hardware reset input (RESET#)
– Hardware method to reset the device for reading array data
*CMOS compatible inputs and outputs
*Package
– 48-ball Very Thin FBGA (S29NS128J)
– 44-ball Very Thin FBGA (S29NS064J, S29NS032J, S29NS016J)
*Cycling Endurance: 1 million cycles per sector typical
*Data Retention: 20 years typical

S29NS128J0LBAW000, S29NS064J0LBAW000, S29NS032J0LBAW000

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Description
The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The NAND512R3A2C, NAND512R4A2C, NAND512W3A2C, and NAND512W4A2C have a density of 512 Mbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A Write Protect pin is available to give a hardware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the following packages:
*TSOP48 12 x 20mm
*VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch)
In order to meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
All devices have the Chip Enable Don't Care option, which allows the code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation.
A Serial Number option, allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.

Features
*High density NAND Flash memories
– 512 Mbit memory array
– Cost effective solutions for mass storage applications
*NAND interface
– x 8 or x 16 bus width
– Multiplexed Address/ Data
*Supply voltage: 1.8 V, 3.0 V
*Page size
– x 8 device: (512 + 16 spare) bytes
– x 16 device: (256 + 8 spare) words
*Block size
– x 8 device: (16 K + 512 spare) bytes
– x 16 device: (8 K + 256 spare) words
*Page Read/Program
– Random access: 12 μs (3 V)/15 μs (1.8 V) (max)
– Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)
– Page Program time: 200 μs (typ)
*Copy Back Program mode
*Fast Block Erase: 2 ms (typ)
*Status Register
*Electronic signature
*Chip Enable ‘don’t care’
*Serial Number option
*Hardware Data Protection
– Program/Erase locked during Power transitions
*Data integrity
– 100,000 Program/Erase cycles (with ECC)
– 10 years Data Retention
*ECOPACK® packages
*Development tools
– Error Correction Code models
– Bad Blocks Management and Wear Leveling algorithms
– Hardware simulation models

NAND512R4A2C, NAND512W3A2C, NAND512W4A2C

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Description
The T89C51AC2 is a high performance CMOS FLASH version of the 80C51 CMOS single chip 8-bit microcontrollers. It contains a 32Kbytes Flash memory block for program and data.
The 16K bytes or 32K bytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.
The T89C51AC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the T89C51AC2 has a 10 bits A/D converter, a 2Kbytes Boot Flash Memory, 2 Kbytes EEPROM for data, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer and a more versatile serial channel that facilitates multiprocessor communication (EUART).
The fully static design of the T89C51AC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.
The T89C51AC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.
The added features of the T89C51AC2 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabilities such as industrial control, consumer goods, alarms, motor control, ...
While remaining fully compatible with the 80C51 it offers a superset of this standard microcontroller. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Features
*80C51 core architecture:
*256 bytes of on-chip RAM
*1Kbytes of on-chip XRAM
*32 Kbytes of on-chip Flash memory
*2 Kbytes of on-chip Flash for Bootloader
*2 Kbytes of on-chip EEPROM
*14-source 4-level interrupt
*Three 16-bit timer/counter
*Full duplex UART compatible 80C51
*maximum crystal frequency 40 MHz. In X2 mode, 20 MHz (CPU core, 40 MHz)
*Five ports: 32 + 2 digital I/O lines
*Five channel 16-bit PCA with:
- PWM (8-bit)
- High-speed output
- Timer and edge capture
*Double Data Pointer
*21 bit watchdog timer (including 7 programmable bits)
*A 10-bit resolution analog to digital converter (ADC) with 8 multiplexed inputs
*20 microsecond conversion time
*Two conversion modes
*On-chip emulation Logic (enhanced Hook system)
*Power saving modes:
*Idle mode
*Power down mode
*Power supply: 5V +/- 10% (or 3V** +/- 10%)
*Temperature range: Industrial (-40 to +85C)
*Packages: TQFP44, PLCC44

T89C51AC2-RLSC-M, T89C51AC2-SLSC-M, T89C51AC2-RLTC-M
TAG A/D, EEPROM, Flash, MCU

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General Description
The A29L160 is a 16Mbit, 3.0 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L160 is offered in 48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L160 can also be programmed in standard EPROM programmers.
The A29L160 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L160 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L160 also offers the ability to program in the Erase Suspend mode. The standard A29L160 offers access times of 70, 90 and 120ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE ) and output enable (OE ) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The A29L160 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L160 is fully erased when shipped from the factory. The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

Features
*Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors
*Access times:
- 70/90/120 (max.)
*Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
*Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors
*Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple program command sequence
*Top or bottom boot block configurations available
*Embedded Algorithms
- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
- Embedded Program algorithm automatically writes and verifies data at specified addresses
*Typical 100,000 program/erase cycles per sector
*20-year data retention at 125°C
- Reliable operation for the life of the system
*CFI (Common Flash Interface) compliant
- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
*Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply Flash memory standard
- Superior inadvertent write protection
*Data Polling and toggle bits
- Provides a software method of detecting completion of program or erase operations
*Ready / BUSY pin (RY / BY)
- Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP)
*Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
*Hardware reset pin (RESET )
- Hardware method to reset the device to reading array data
*Package options
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
- All Pb-free (Lead-free) products are RoHS compliant

A29L160TM-70, A29L160TV-70, A29L160TV-70F, A29L160TG-70, A29L160TM-90, A29L160TV-90, A29L160TG-90, A29L160TM-120, A29L160TV-120, A29L160TG-120

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Description
Xilinx introduces the QPro™ XQ18V04 Military Grade 4Mbit in-system programmable configuration Flash PROM. The XQ18V04 is a 3.3V rewritable PROM that provides a reliable non-volatile method for storing large Xilinx FPGA configuration bitstreams used in systems that
require operation over the full military temperature range.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in SelectMAP mode (Slave), an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data
is available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are
interconnected. The XQ18V04 is compatible and can be cascaded with other configuration PROMs such as the XQR1701L and XQR17V16 one-time programmable configuration
PROMs.

Features
*Operating Temperature Range: –55° C to +125°C
*Low-power advanced CMOS FLASH process memory cells immune to static single event upset
*In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
*IEEE Std 1149.1 boundary-scan (JTAG) support
*Cascadable for storing longer or multiple bitstreams
*Dual configuration modes
- Serial Slow/Fast configuration (up to 20 MHz)
- Parallel (up to 160 Mbps at 20 MHz)
*5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
*3.3V or 2.5V output capability
*Available in plastic VQ44 packaging only
*Design support using the Xilinx Alliance Series™ and Xilinx Foundation Series™ software packages
*JTAG command initiation of standard FPGA configuration

XQV300, XQV600, XQV1000

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