Introduction
The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.

Features
*2,910 to 20,060 LEs
*Up to 294,912 RAM bits (36,864 bytes)
*Supports configuration through low-cost serial configuration device
*Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
*Support for 66-MHz, 32-bit PCI standard
*Low speed (311 Mbps) LVDS I/O support
*Up to two PLLs per device provide clock multiplication and phase shifting
*Up to eight global clock lines with six clock resources available per logic array block (LAB) row
*Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM
*Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions

EP1C3F400, EP1C4F400m EP1C6F400, EP1C12F400

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General Description
 Altera® ACEX 1K devices provide a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs.
LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
These elements make ACEX 1K suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation and microcontrollers, as required in high-performance communications applications.
Based on reconfigurable CMOS SRAM elements, the ACEX 1K architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components.
The advanced process and the low voltage requirement of the 2.5-V core allow ACEX 1K devices to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches.
The ability to reconfigure ACEX 1K devices enables complete testing prior to shipment and allows the designer to focus on simulation and design verification.
ACEX 1K device reconfigurability eliminates inventory management for gate array designs and test vector generation for fault coverage.
ACEX 1K device performance for some common designs.
All performance results were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file.

Features
* Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 10,000 to 100,000 typical gates
- Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity)
* Cost-efficient programmable architecture for high-volume applications
- Die size reductions via hybrid process
- Low cost solution for high-performance communications applications
* System-level features
- MultiVolt™ I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
- Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2 for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic.
- Operate with a 2.5-V internal supply voltage
- In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port
- ClockLock TM and ClockBoost TM options for reduced clock delay, clock skew, and clock multiplication
- Built-in, low-skew clock distribution trees
- 100% functional testing of all devices; test vectors or scan chains are not required
- Pull-up on I/O pins before and during configuration
* Flexible interconnect
- FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays
- Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)
- Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)
- Tri-state emulation that implements internal tri-state buses
- Up to six global clock signals and four global clear signals
* Powerful I/O pins
- Individual tri-state output enable control for each pin
- Open-drain option on each I/O pin
- Programmable output slew-rate control to reduce switching noise
- Clamp to V CCIO user-selectable on a pin-by-pin basis
- Supports hot-socketing
* Software design support and automatic place-and-route provided by Altera’s MAX+PLUS®
II development system for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations
* Flexible package options are available in 100 to 484 pins, including the innovative FineLine BGA TM packages
* Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic

EP1K10
EP1K30
EP1K50
EP1K100

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General Description
 The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture.
Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Features
* High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
* 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
* Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
* Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
* Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates
* 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
* PCI-compliant devices available
* Open-drain output option in MAX 7000S devices
* Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
* Programmable power-saving mode for a reduction of over 50% in each macrocell
* Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
* 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
* Programmable security bit for protection of proprietary designs
* 3.3-V or 5.0-V operation
– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
* Enhanced features available in MAX 7000E and MAX 7000S devices
– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
– Programmable output slew-rate control
* Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations

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Features...
■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
■ High–density PLDs ranging from 600 to 10,000 usable gates
■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages
■ Hot–socketing support
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ Industrial temperature range
■ PCI compatible
■ Bus–friendly architecture including programmable slew–rate control
■ Open–drain output option
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable power–saving mode for a power reduction of over 50% in each macrocell
■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ Enhanced architectural features, including:
– 6 or 10 pin– or logic–driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Programmable output slew–rate control
■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)

General Description
MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.

EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A

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