General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L16181, A67L06361 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/LD ), synchronous clock enable ( CEN ), byte write enables (BW1,BW2,BW3,BW4) and read/write (R/W).
Asynchronous inputs include the output enable (OE), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state.
Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded.
The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.

Features
*Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz)
*Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization
*Signal +3.3V ± 5% power supply
*Individual Byte Write control capability
*Clock enable ( CEN) pin to enable clock and suspend operations
*Clock-controlled and registered address, data and control signals
*Registered output for pipelined applications
*Three separate chip enables allow wide range of options for CE control, address pipelining
*Internally self-timed write cycle
*Selectable BURST mode (Linear or Interleaved)
*SLEEP mode (ZZ pin) provided
*Available in 100 pin LQFP package

A67L06361, A67L16181E-6.5, A67L16181E-7.5, A67L16181-8.5

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GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion CE2#, CE2), burst control inputs (ADSC#, ADSP#,ADV#), byte write enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version.
Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs.
Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#).
Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd# controls DQd’s and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions.
Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. Users can choose either a 3.3V or 2.5V I/O version. The device is ideally suited for 486, Pentium®, 680x0 and PowerPC systems and those systems that benefit from a wide synchronous data bus.
The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications.

FEATURES
*Fast clock and OE# access times
*Single +3.3V +0.3V/-0.165V power supply (VDD)
*Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
*SNOOZE MODE for reduced-power standby
*Common data inputs and data outputs
*Individual BYTE WRITE control and GLOBAL WRITE
*Three chip enables for simple depth expansion and address pipelining
*Clock-controlled and registered addresses, data I/Os and control signals
*Internally self-timed WRITE cycle
*Burst control (interleaved or linear burst)
*Automatic power-down for portable applications
*100-pin TQFP package
*165-pin FBGA
*Low capacitive bus loading
*x18, x32, and x36 versions available

MT58L512L18F, MT58L256L32F, MT58L256L36F, MT58L512V18F, MT58L256V32F

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