Designed specifically to address high-end embedded applications for storage, the PowerPC 440SP Embedded Processor (PPC440SP) provides a highperformance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation.
This chip contains a high-performance RISC processor core, a DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three DDR PCI-X bus interfaces, an Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O.

*PowerPC‚ 440 processor core operating at up to 667MHz with 32-KB I- and D-caches (with parity checking)
*On-chip 256-KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory
*Selectable Processor:Bus clock ratios (Refer to the Clocking chapter in the PPC440SP Embedded Processor User’s Manual for details)
*Supports up to 4 GB (2 Chip Selects) of 64-bit/32-bit SDRAM with ECC
– DDR1 266-333-400
– DDR2 400-533-667
*Three DDR PCI-X interfaces (32-bit or 64-bit) up to 133 MHz (DDR 266) with support for
conventional PCI
*XOR Accelerator with DMA controller
*Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P &
Q parity computations, supports up to 255 drives
*I2O Messaging Unit with two DMA controllers
*External Peripheral Bus (24-bit Address, 8-bit Data) for up to three devices
*One Ethernet 10/100/1000 Mbps half- or fullduplex interface. Operational modes supported
are MII and GMII.
*Programmable Interrupt Controller supports interrupts from a variety of sources.
*Programmable General Purpose Timers (GPT)
*Three serial ports (16750 compatible UART)
*Two IIC interfaces
*General Purpose I/O (GPIO) interface available
*JTAG interface for board level testing
*Processor can boot from PCI memory


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*Intel Pentium III/Celeron and VIA C3 processor 566MHz~1.26GHz
*Supports 100/133MHz FSB
*Two DIMM sockets with a max. capacity of 1GB
*VIA VT8606/VT82C686B system chipset
*VIA VT82C686B, SMC SP37E760 super I/O chipset
*VIA VT8606 graphics controller
*Four RealTek RTL8100B or Intel 82559 fast Ethernet controller
*AC97 3D audio controller
*Fast PCI ATA/33/66/100 IDE controller
*Four COM, four USB ports
*Hardware Monitor function
*TV-Out function (optional)

HS-4650(8100B), HS-4650LLV(8100B), HS-4650(82559), HS-4650LLV(82559)

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General Description
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions.
With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification.
FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage.
Table 5 shows FLEX 10KE performance for some common designs.
All performance values were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or chematic design file.

* Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 30,000 to 200,000 typical gates (see Tables 1 and 2)
- Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
* System-level features
- MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (tSU and tCO) up to 212 MHz
- Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic


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* Member of the E86™ CPU series
– 16-bit data bus
– 24-bit address bus
– 16-Mbyte address range
– Long-term stable supply from AMD
* 40-, 33- and 25-MHz operating speeds
* Ideal for embedded applications
– True Static design for low-power applications
– 3–5 V operation (at 25 MHz)
– Ideal for cost-sensitive designs
– True DC (0 MHz) operation
* Industry Standard Architecture
– Supports world’s largest software base for x86 architectures
– Wide range of chipsets and BIOS available
– Fully compatible with all 386SX systems and software
* System Management Mode (SMM) for system and power management (Am386SXLV only)
– System Management Interrupt (SMI) for power management independent of processor operating mode and operating system
– SMI coupled with I/O instruction break feature provides transparent power off and auto resume of peripherals which may not be “power aware”
– SMI is non-maskable and has higher priority than Non-Maskable Interrupt (NMI)
– Automatic save and restore of the microprocessor state
* 100-lead Plastic Quad Flat Pack (PQFP) package
* Extended temperature version available

The Am386®SX/SXL/SXLV microprocessors are lowcost, high-performance CPUs for embedded applications.
Embedded customers benefit from using the Am386 microprocessor in a number of ways.
The Am386SX/SXL/SXLV microprocessors provide embedded customers access to very inexpensive processors and the highest performance of any 386SX available anywhere. The 16-bit data path allows for inexpensive memory design. Full static operation, coupled with 3-V supplies, benefit customers who desire low-power designs. Standby Mode allows the Am386SXL/SXLV microprocessors to be clocked down to 0 MHz (DC) and retain full register contents. A float pin places all outputs in a three-state mode to facilitate board test and debug. Additionally, the Am386SXLV microprocessor comes with System Management Mode (SMM) for system and power management. SMI (System Management Interrupt) is a non-maskable, higher priority interrupt than NMI and has its own code space (1 Mbyte in Real Mode and 16 Mbyte in Protected Mode). SMI can be coupled with the I/O instruction break feature to implement transparent power management of peripherals.
SMM can be used by system designers to implement system and power management code independent of the operating system or the processor mode. Since the Am386SX/SXL/SXLV microprocessors are supported as an embedded product in the E86 family, customers can rely on long-term supply of product, and extended temperature products.
In addition, customers have access to the largest selection of inexpensive development tools, compilers, and chipsets. A large number of PC operating systems and Real Time Operating Systems (RTOS) support the Am386SX/SXL/SXLV microprocessors. This means cheaper development costs, and improved time to market.
The Am386SX/SXL/SXLV microprocessor is available in a small footprint 100-pin Plastic Quad Flat Pack (PQFP) package.


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• PowerNP™ technology using an AMCC PowerPC ® 405 32-bit RISC processor core operating up to 266 MHz
• PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
• External bus for peripheral devices
- Flash and ROM interface
- Direct support for 8-, or 16-, or 32-bit SRAM and external peripherals
- Up to 8 devices
- External mastering supported
• DMA support for external peripherals, internal UARTs and memory
- Scatter-gather chaining supported
- Four channels
• PCI Revision 2.2 compliant interface (32-bit, up to 66MHz)
- Asynchronous PCI bus interface
- Internal PCI bus arbiter which can be disabled for use with an external arbiter
• Four 10/100 Ethernet MACs supporting up to four external PHYs via MII, RMII, or SMII interfaces
• HDLC interface with 32 channels through two ports at up to 4.096 Mbps each or 8.192 Mbps
for a single port
• HDLC interface with 8 channels through 8 ports at 2.048 Mbps maximum
• Programmable interrupt controller
- Seven external and 49 internal
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor core
- Programmable critical interrupt priority ordering
- Programmable critical interrupt vector
• Programmable timers
• Two serial ports (16550 compatible UART)
• One IIC interface
• General Purpose I/O (GPIO) available
• Supports JTAG for board level testing
• Internal processor local bus (PLB) runs at SDRAM interface frequency
• Supports PowerPC processor boot from PCI memory
• User accessible performance counters

Designed specifically to address embedded applications, the NPe405H provides a high-performance, lowpower solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements.
This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus bridge, Ethernet EMACs, HDLC controllers, external bus controller for ROM, Flash, and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose
Technology: CMOS SA-12E 0.25 μm 0.18 μm Leff)
Package: 35mm, 580-ball enhanced plastic ball grid array (E-PBGA)
Power (typical): 2.3W at 133MHz, 2.9W at 200MHz, 3.4W at 266MHz


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