The PI90SD1636C is a single chip, Gigabit Ethernet transceiver. It performs all the functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specifi ed by the IEEE
802.3z Gigabit Ethernet standard. These functions include parallelto-serial and serial-to-parallel conversion, clock gen er a tion, clock data re cov ery, and word synchronization. In addition, an internal loopback function is provided for system debugging.
The PI90SD1636C is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point applications. The device supports 1000BASE-LX and 1000BASE-SX fi ber-optic media, and 1000BASE-CX copper media.
The transmitter section of the PI90SD1636C accepts 10-bit wide parallel TTL data and converts it to a high speed serial data stream. The parallel data is encoded in 8b/10b format. This incoming parallel data is latched into an input register, and synchronized on the rising edge of the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125 MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used to provide the high speed serial data output. The output is sent through a Pseudo Emitter Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of 1000BASE-CX medium, or to a fi ber optic module in the case of 1000BASE-LX or 1000BASE SX fi ber optic medium.
The receiver section of the PI90SD1636C accepts a serial PECLcom pat i ble data stream at a 1.25 Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A PLL locks onto the incoming serial data stream, and recovers the 1.25 GHz high speed serial clock and data. This is accomplished by contin u al ly frequency locking onto the 125 MHz reference clock, and by phase locking onto the incoming data stream. The serial data is converted back to parallel data format. The ‘comma’ character is used to establish byte alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are alternately used to clock out the parallel data on the rising edge. This parallel data is sent to the user in TTL-compatible form.

* IEEE 802.3z Gigabit Ethernet Compliant
*Supports 1.25 Gbps Using NRZ Coding over uncompensated twin coax cable
*Fully integrated CMOS IC
*Low Power Consumption
*ESD rating >2000V (Human Body Model) or > 200V (Machine Model)
*5-Volt Input Tolerance
*Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A and Vitesse VSC7123 transceivers (see Appendix A)
*Packaging (Pb-free & Green available):
-64-pin LQFP (FC)
-64-pin LQFP (FD)

*Gigabit Ethernet
*Serial Backplane
*Proprietary point-to-point applicaitons
*Passive Optical Networks

PI90SD1636CFC, PI90SD1636CFCE, PI90SD1636CFD, PI90SD1636CFDE

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The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber optic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a lowspeed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW.
The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip.

*Operating rate
*1250 MHz (Gigabit Ethernet) line rates
*Half and full VCO output rates
*Functionally compliant IEEE 802.3z Gigabit Ethernet standard
*Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference
*Receiver PLL provides clock and data recovery
*10-bit parallel TTL compatible interface
*Low-jitter serial LVPECL compatible interface
*Local loopback
*Single +3.3 V supply, 620 mW power dissipation
*64 PQFP or TQFP package
*Continuous downstream clocking from receiver
*Drives 30 m of Twinax cable directly

*Frame buffer
*Switched networks
*Data broadcast environments
*Proprietary extended backplanes

S2060A, S2060B, S2060C, S2060D

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*20 10-GbE/1-GbE ports
*Based on StrataXGS™ field-proven, robust architecture
*Integrated high-performance SerDes
-Integrated XAUI™ SerDes for all 20 10-GE ports
-Uses single SerDes lane per port at GE speeds
*200-Gbps switching capacity at line rate
*Support for eight classes of service (CoS) per port
*Support for Deficit Round Robin, Weighted Round Robin and Strict priority scheduling
*Support for a cut-through switching mode
*Port trunking and remote mirroring support
*Fully integrated data and address memory on a single chip
*Advanced packet flow control
-Head of line blocking prevention
-Full-duplex flow control (802.3x)
*ContentAware™ network processing per port
-Line rate multifield packet classification
-Supports IEEE 802.1p, TOS/DiffServ, rate limiting, policing, priority tagging, and remapping
-Extended security and ACL filtering
*Full IPv6 routing support
*Enhanced security and management capabilities
*Low power consumption

*High level of integration and low power consumption enable system vendors to build high-performance, high-port-density 10-Gigabit Ethernet switches in the same form factor as existing GE solutions.
*Built-in, high-speed serial interfaces with integrated memory eases and accelerates system design, while reducing cost and conserving board space.
*Built-in Layer 3 routing support enables embedded switch to become an extension of the enterprise core network.
*Advanced load balancing and strong user isolation features facilitate the implementation of utility computing services.
*Integrated security features and enhanced management capabilities improve network reliability and lower cost of ownership for BCM56800-based solutions.
*Broadcom switch API compatibility enables software reuse and faster time to market.

*Embedded switch in next-generation 10GE Blade Servers
*10-GE/1-GE switching engine in advanced TCA chassis platforms
*Multilayer switch in high-density 10-Gigabit Ethernet switches

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The Am79761 Gigabit Ethernet Physical Layer Serializer/Deserializer (GigaPHY-SD) device is a 1.25 Gbps Ethernet Transceiver optimized for Gigabit Ethernet/1000BASE-X applications. It implements the Physical Medium Attachment (PMA) layer for a single port.
The GigaPHY-SD device can interface to fiber-optic media to support 1000BASE-LX and 1000BASE-SX applications and can interface to copper coax to support 1000BASE-CX applications.
The functions performed by the device include serializing the 8B/10B 10-bit data for transmission, deserializing received code groups, recovering the clock from the incoming data stream, and word synchronization.
When transmitting, the GigaPHY-SD device receives 10-bit 8B/10B code groups at 125 million code groups per second. It then serializes the parallel data stream, adding a reference clock, and transmits it through the PECL drivers.
When receiving, the GigaPHY-SD device receives the PECL data stream from the network. It then recovers the clock from the data stream, deserializes the data stream into a 10-bit code group, and transmits it to the Physical Coding Sublayer (PCS) logic above. Optionally, it detects comma characters used to align the incoming word.

*Gigabit Ethernet Transceiver operates at 1.25 Gigabits per second (Gbps)
*Suitable for both Coaxial and Optical Link applications
*10-bit TTL Interface for Transmit and Receive Data
*Monolithic Clock Synthesis and Clock Recovery requires no external components
*Word Synchronization Function (Comma Detect)
*Low Power Operation - 700 mW typical
*64-pin Standard PQFP
-14 x 14 mm (0° C - 70° C)
-10 x 10 mm (0° C - 50° C)
*125 MHz TTL Reference Clock
*Loopback Diagnostic
*Single +3.3 V Supply

AM79761YC-10, AM79761YC-14

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General Description
The LXT9781 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical
layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent
Interface (RMII) for switching and other independent port applications. The LXT9761 offers the
same features and functionality in a six-port device. This data sheet uses the singular designation “LXT97x1” to refer to both devices.
All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for
a 10/100BASE-TX or 100BASE-FX connection.
The LXT97x1 provides three discrete LED driver outputs for each port, as well as eight global
serial LED outputs. The device supports both half- and full-duplex operation at 10 Mbps and 100Mbps, and requires only a single 3.3V power supply.

Product Features
*Six or eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters
*3.3V operation
*Optimized for dual-high stacked R45 applications
*Proprietary Optimal Signal Processing™ architecture improves SNR by 3 dB over ideal analog filters
*Robust baseline wander correction 100BASE-FX fiber-optic capability on all ports
*Supports both auto-negotiation and legacy systems without auto-negotiation capability
*JTAG boundary scan
*Multiple Reduced MII (RMII) ports for independent PHY port operation
*Configurable via MDIO port or external control pins.
*Maskable interrupts
*Low power consumption (390 mW per port, typical)
*208-pin PQFP (LXT9761 and LXT9781)
*272-pin PBGA (LXT9781 only)

*100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs.


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The BCM56580 network switch is a high-density, 2.5-Gigabit Ethernet switching chip solution with 20 ports. Additionally, the BCM56580 integrates all the SerDes required to interface to applicable copper and fiber physical interfaces. The integrated SerDes functionality includes 10-Gbps XAUI interfaces and 2.5/1-Gbps SGMII PHY interfaces. The integrated SerDes complies with the CX-4 standard and PICMG3.1 standard, which ensures interoperability with Ethernet line cards in an advanced TCA chassis.
With 80 Gbps of aggregate switching bandwidth, BCM56580 represents a high level of Ethernet switching integration that enables embedded switching vendors to extend the life of their  existing GbE system designs by providing a performance upgrade using the same physical enclosures and backplanes. This ability has many benefits, including reducing the vendor development cost and creating additional value in current generation systems through upgradability.
The BCM56580's low power dissipation simplifies board design and optimizes vendor board space.
The advanced ContentAware engine supports ToS/DiffServ, policybased routing, priority tagging, and remapping. The advanced packet filtering and classification functions of the BCM56580 make it ideal for Utility computing applications, where user segregation and network
security is critical.
In addition, the BCM56580 provides advanced security features that improve network resiliency and reliability. Moreover, the BCM56580 features advanced load balancing functionality that uses flow information to provide high-percentage link utilization.
The BCM56580 supports L2 switching with 4K VLANs, IPv4 and IPv6 full routing functionality, enabling it to become a direct extension of the enterprise network. This provides additional value to customers by eliminating the hardware and management cost of having intermediate
As the latest member of the StrataXGS switch family, the BCM56580 Software Development Kit preserves software continuity with Gigabit Ethernet switches, reducing development cost and shortening the product time-to-market.
The BCM56580 implements congestion handling features such as Head- Of-Line blocking prevention and IEEE 802.3x flow control.
In addition to a 32-bit PCI interface used to communicate with a local CPU, the BCM56580 supports an I2C controller for communicating with external devices such as serial EEPROM, flash memories, and parallel port devices.
The BCM56580 relies on Broadcom’s modular switching architecture to provide intelligent packet processing, network security, and enhanced manageability at a low cost. The BCM56580 is an ideal solution for nextgeneration, high-speed, embedded switching applications, such as Blade Servers and advanced TCA chassis platforms.

*16 × 2.5-GbE/1-GbE and 4 × 10-GbE/2.5-GbE/1-GbE ports
*Based on StrataXGS® field-proven, robust architecture
*Integrated high-performance SerDes
- Integrated XAUI™ SerDes for all 10-GbE ports
- Integrated single-lane SerDes for all 2.5-GbE ports
*80-Gbps switching capacity at line rate
*Support for eight classes of service (CoS) per port
*Support for Deficit Round Robin, Weighted Round Robin, and Strict priority scheduling
*Support for a cut-through switching mode
*Port trunking and remote mirroring support
*Fully integrated data and address memory on a single chip
*Advanced packet flow control
- Head of line blocking prevention
- Full-duplex flow control (802.3x)
*ContentAware™ network processing per port
- Line rate multifield packet classification
- Supports IEEE 802.1p, TOS/DiffServ, rate limiting, policing, priority tagging, and remapping
- Extended security and ACL filtering
*Full IPv6 routing support
*Enhanced security and management capabilities
*Low power consumption

*Embedded switch in next-generation 2.5 GbE Blade Servers
*2.5 GbE/1 GbE switching engine in advanced TCA chassis platforms
*Embedded switch to enhance performance of existing Gigabit Ethernet Blade Servers or advanced TCA chassis

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General Description
 The LAN9215i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required.
The LAN9215i has been architected to provide the best price-performance ratio for any 16-bit application with medium performance requirements.
The LAN9215i is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.
The LAN9215i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface.
The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus.
The LAN9215i includes large transmit and receive data FIFOs to accommodate high latency applications.
In addition, the LAN9215i memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity.

* Optimized for medium performance applications
* Efficient architecture with low CPU overhead
* Easily interfaces to most 16-bit embedded CPU’s
* Integrated PHY with HP Auto-MDIX
* Supports audio & video streaming over Ethernet: multiple standard-definition (SD) MPEG2 streams
* Compatible with other members of LAN9218 family
Target Applications
* Basic cable, satellite, and IP set-top boxes
* Digital video recorders
* Video-over IP solutions, IP PBX & video phones
* Wireless routers & access points
* Audio distribution systems
* Printers, kiosks, security systems
* General embedded applications
Key Benefits
* Non-PCI Ethernet controller for medium performance
- 16-bit interface
- Burst-mode read support
- External MII Interface
* Eliminates dropped packets
- Internal buffer memory can store over 200 packets
- Automatic PAUSE and back-pressure flow control
* Minimizes CPU overhead
- Supports Slave-DMA
- Interrupt Pin with Programmable Hold-off timer
* Reduces system cost and increases design flexibility
* SRAM-like interface easily interfaces to most embedded CPU’s or SoC’s
* Reduced Power Modes
- Numerous power management modes
- Wake on LAN*
- Magic packet wakeup*
- Wakeup indicator event signal
- Link Status Change
* Single chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u standards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and checking
- Automatic payload padding and pad removal
- Loop-back modes
* Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
* Integrated 10/100 Ethernet PHY
- Supports HP Auto-MDIX
- Auto-negotiation
- Supports energy-detect power down
* High-Performance host bus interface
- Simple, SRAM-like interface
- 16-bit data bus
- 16Kbyte FIFO with flexible TX/RX allocation
- One configurable host interrupt
* Miscellaneous features
- Low-profile 100-pin TQFP, lead-free RoHS Compliant package
- Integrated 1.8V regulator
- General Purpose Timer
- Optional EEPROM interface
- Support for 3 status LEDs multiplexed with Programmable GPIO signals
* Single 3.3V Power Supply with 5V tolerant I/O
* -40°C to +85°C Industrial Temperature Support

The LAN9215i is well suited for many medium-performance embedded applications, including:
* Printers, kiosks, POS terminals and security systems
* Audio distribution systems
* General embedded systems
* Basic cable, satellite and IP set-top boxes
* Voice-over-IP solutions

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· IEEE 802.3u 100BASE-T, TX, and T4 Compatible
· Single chip PCMCIA bus 10/100Mbps Fast Ethernet MAC Controller
· Embedded 8K * 16 bit SRAM
· NE2000 register level compatible instruction
· Compliant with 16 bit PC Card Standard - February 1995
· Support both 10Mbps and 100Mbps data rate
· Support both full-duplex or half-duplex operation
· Provides a MII port for both 10/100Mbps operation
· Provides SNI I/F for Home LAN PHY or 10M transceiver option
· Support 128/256 bytes EEPROM (used for saving CIS)
· Support automatic loading of Ethernet ID, CIS and Adapter Configuration from EEPROM on power-on initialization
· External and internal loop-back capability
· Support 8 General Purpose I/O ports
· 128-pin LQFP low profile package
· 20MHz to 25MHz Operation, Dual 5V and 3.3V CMOS process with 5V I/O tolerance. Or pure 3.3V operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of their respective holders.

Product description
The AX88190A Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus Ethernet Controller with embedded 8K*16 bit SRAM. The AX88190A contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card Standard – February 1995. The AX88190A implements both 10Mbps and 100Mbps Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard. The AX88190A supports 10Mbps/100Mbps media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the design. Using Serial Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be supported. The AX88190A is built in interface to connect FAX/MODEM chipset with parallel bus interface.

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*Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port
*Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards
*84-pin PLCC and 100-pin PQFP Packages
*80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as
*Modular architecture allows easy tuning to specific applications
*High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer
*Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency
and support the following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of collision frames
— Automatic retransmission with no FIFO reload
*Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs
*Direct FIFO read/write access for simple interface to DMA controllers or l/O processors
*Arbitrary byte alignment and little/big endian memory interface supported
*Internal/external loopback capabilities
*External Address Detection Interface (EADI) for external hardware address filtering in
bridge/router applications
*JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test
*Integrated Manchester Encoder/Decoder
*Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI)
*Supports the following types of network

— AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU
— DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU
— General Purpose Serial Interface (GPSI) to external encoding/decoding scheme
— Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port
*Sleep mode allows reduced power consumption for critical battery powered applications
*5 MHz-25 MHz system clock speed
*Support for operation in industrial temperature range (–40°C to +85°C) available in all three

The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specifically designed to address applications where multiple I/O peripherals are present, and a centralized or system
specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an external DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers.
The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architecture and versatile system interface allow the MACE
device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system.


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• Fifth generation of StrataSwitch® and StrataXGS® product line
• 24 10/100/1000 Mbps Ethernet ports supporting SGMII and SerDes interfaces for both copper and fiber connections
• The BCM56510 device, is a powerful, highly-integrated member of the scalable StrataXGS III product family
• Line-rate switching for all packet sizes and conditions
• On-chip data packet memory and table memory
• IPv6 routing and tunneling
• Advanced ContentAware™ classification Filtering Processors (FP)
• Advanced security features in hardware
• Port-trunking and mirroring supported across stack
• Advanced packet flow control:
• Head-of-line blocking prevention
• Back pressure support
• Eight QoS queues per port with hierarchical minimum/ maximum shaping per Classes of Service (CoS) per queue per port
• Standard compliant 802.1ad provider bridging

• Highly scalable BroadScale™ architecture evolved from five generations of switching experience provides rich features, scalability, and future proof solutions.
• Optimized for secure switching and convergence of wired and wireless applications and services in networks
• System vendors can build scalable high-performance, high-port density GbE LAN switches in several form factors.
• Multiple CoS and low latency enable the support of VoIP and triple play services.
• Built-in high-speed serial interfaces with Broadcom-unique SerDes technology ease and accelerate system design, while reducing cost and conserving board space.
• Broadcom switch API compatibility enables software reuse and faster time-to-market.
• Small package and low power enables cost-effective and highperformance system design.

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