DESCRIPTION
The AZ10/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101, the EL01 is ideally suited for those applications that require the ultimate in AC performance.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*230ps Propagation Delay
*High Bandwidth Output Transitions
*75kΩ Internal Input Pulldown Resistors
*Direct Replacement for ON Semiconductor MC10EL01 & MC100EL01

AZ100EL01

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DESCRIPTION
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*700 MHz Minimum Shift Frequency
*9-Bit for Byte-Parity Application
*Asynchronous Master Reset
*Dual Clocks
*Operating Range of 4.2V to 5.46V
*75kΩ Internal Input Pulldown Resistors
*Direct Replacement for ON Semi MC10E142 & MC100E142

AZ100E142, AZ10E142FN, AZ100E142FN

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DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs.
Each flip-flop may be locked separately by holding Common Clock (CC) LOW and using the Clock Enable (C¯¯En) inputs for clocking.
Common clocking is achieved by holding the C¯¯En inputs LOW and using CC to clock all four flip-flops.
In this case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn).
Asynchronous set controls (Sn) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both CC and C¯¯En are LOW, and transfers to the slave when either CC or C¯¯En (or both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
* 1100 MHz Min. Toggle Frequency
* Differential Outputs
* Individual and Common Clocks
* Individual Resets (asynchronous)
* Paired Sets (asynchronous)
* Operating Range of 4.2V to 5.46V
* 75kΩ Internal Input Pulldown Resistors
* Direct Replacement for On Semiconductor MC10E131 & MC100E131

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