DESCRIPTION
The GAL22LV10D, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

FEATURES
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-4 ns Maximum Propagation Delay
-Fmax = 250 MHz
-3 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
*3.3V LOW VOLTAGE 22V10 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
-I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C)
*ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*TEN OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION 22LV10D

GAL22LV10D-4LJ, GAL22LV10D-5LJ, GAL22LV10C-7LJ, GAL22LV10C-10LJ

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Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.5 ns Maximum Propagation Delay
-Fmax = 250 MHz
-2.5 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
-TTL-Compatible Balanced 8mA Output Drive
*3.3V LOW VOLTAGE 20V8 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
*ACTIVE PULL-UPS ON ALL PINS
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL20LV8D-3LJ, GAL20LV8D-5LJ, GAL20LV8D-7LJ

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Description
The GAL20V8Z and GAL20V8ZD, at 100 μA standby current and 12ns propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL20V8Z/ZD is manufactured using Lattice Semiconductor's advanced zero power E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
The GAL20V8Z uses Input Transition Detection (ITD) to put the device in standby mode and is capable of emulating the full functionality of the standard GAL20V8. The GAL20V8ZD utilizes a dedicated power-down pin (DPP) to put the device in standby mode. It has 19 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
*ZERO POWER E2CMOS TECHNOLOGY
-100μA Standby Current
-Input Transition Detection on GAL20V8Z
-Dedicated Power-down Pin on GAL20V8ZD
-Input and Output Latching During Power Down
*HIGH PERFORMANCE E2CMOS TECHNOLOGY
-12 ns Maximum Propagation Delay
-Fmax = 83.3 MHz
-8 ns Maximum from Clock Input to Data Output
-TTL Compatible 16 mA Output Drive
-UltraMOS® Advanced CMOS Technology
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
-Architecturally Similar to Standard GAL20V8
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Battery Powered Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
*ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL20V8ZD, GAL20V8Z-12QP, GAL20V8Z-12QJ, GAL20V8ZD-12QP
TAG E2CMOS, PLD, Power

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Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.5 ns Maximum Propagation Delay
-Fmax = 250 MHz
-2.5 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
*3.3V LOW VOLTAGE 16V8 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
-I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
*ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION
*LEAD-FREE PACKAGE OPTIONS

GAL16LV8D-3LJ, GAL16LV8D-5LJ, GAL16LV8C-7LJ, GAL16LV8C-10LJ

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