The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs.

*2.5V or 3.3V operation
*200-MHz clock support
*LVPECL or LVCMOS/LVTTL clock input
*LVCMOS/LVTTL compatible outputs
*15 clock outputs: drive up to 30 clock lines
*1X and 1/2X configurable outputs
*Output three-state control
*350 ps maximum output-to-output skew
*Pin compatible with MPC949, MPC9449
*Available in Commercial and Industrial temperature range
*52-pin TQFP package

CY29949AXI, CY29949AXIT, CY29949AXC, CY29949AXCT

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The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408 provides a low power, low noise, low skew, point-to-point solution for distributing LVDS
clock signals.
Guaranteed output and part-to-part skew specifications make the ICS85408 ideal for those applications demanding well defined performance and repeatability.

*8 Differential LVDS outputs
*CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
*Maximum output frequency: 700MHz
*Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
*Translates any single-ended input signal to LVDS with resistor bias on nCLK input
*Multiple output enable inputs for disabling unused outputs in reduced fanout applications
*Output skew: 50ps (maximum)
*Part-to-part skew: 550ps (maximum)
*Propagation delay: 2.4ns (maximum)
*3.3V operating supply
*0°C to 70°C ambient operating temperature
*Lead-Free package RoHS compliant

ICS85408BG, ICS85408BGT

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