The Si5010 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data rates. DSPLL® technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance in the application.
The Si5010 represents an industry-leading combination of low-jitter, low-power, and small size for high-speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40 to 85 °C).

Complete CDR solution includes the following:
*Supports OC-12/3, STM-4/1
*Low power, 293 mW (TYP OC-12)
*Small footprint: 4x4 mm
*DSPLL™ eliminates external loop filter components
*3.3 V tolerant control inputs
*Exceeds All SONET/SDH jitter specifications
*Jitter generation 1.6 mUIrms (typ)
*Device powerdown
*Loss-of-lock indicator
*Single 2.5 V supply

*SONET/SDH/ATM routers
*Add/drop multiplexers
*Digital cross connects
*Board level serial links
*SONET/SDH test equipment
*Optical transceiver modules
*SONET/SDH regenerators

Si5010-BM, Si5010-GM

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*The 67-21 series is available for orange, green, blue and yellow or other color due to the different raw material.
*Base on the package design, the device result in wide view angle.

*Inner reflector.
*White package.
*Optical indicator.
*P-LCC-2 package.
*Wide viewing angle.
*Colorless clear resin.
*Precondition:Base on JEDEC Level-2.
*ESD:Up to 2KV. (Base JESD22-A114-B)
*The product itself will remain within RoHS compliant version.
*Suitable for vapor-phase reflow, infrared reflow and wave solder processes.

*Automotive backlighting or indicator:Dashboard, switch, audio and video equipments…etc.
*Backlight:LCD, switches, symbol, mobile phone and illuminated advertising.
*Display for indoor and outdoor application:Traffic…etc.
*Ideal for coupling into light guides.
*Substitution of traditional light
*Optical indicator
*General applications.


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The EM44AM1684LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 512Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (12.5mmx10mm, 0.8mm x 0.8mm ball pitch).

*JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
*All inputs and outputs are compatible with SSTL_18 interface.
*Fully differential clock inputs (CK,/CK) operation.
*4 Banks
*Posted CAS
*Burst Length: 4 and 8.
*Programmable CAS Latency (CL): 3, 4 and 5.
*Programmable Additive Latency (AL): 0, 1, 2, 3 and 4.
*Write Latency (WL) =Read Latency (RL) -1.
*Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
*Bi-directional Differential Data Strobe (DQS).
*Data inputs on DQS centers when write.
*Data outputs on DQS, /DQS edges when read.
*On chip DLL align DQ, DQS and /DQS transition with CK transition.
*DM mask write data-in at the both rising and falling edges of the data strobe.
*Sequential & Interleaved Burst type available.
*Off-Chip Driver (OCD) Impedance Adjustment
*On Die Termination (ODT)
*Auto Refresh and Self Refresh
*8,192 Refresh Cycles / 64ms
*Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≦ 95°C
*RoHS Compliance
*Partial Array Self-Refresh (PASR)
*High Temperature Self-Refresh rate enable

EM44AM1684LBA-5F, EM44AM1684LBA-37F, EM44AM1684LBA-3F

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The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.

Functional Description
Cyclone® devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs.
M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM.
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).
Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support.

The Cyclone device family offers the following features:
*2,910 to 20,060 LEs, see Table 1–1
*Up to 294,912 RAM bits (36,864 bytes)
*Supports configuration through low-cost serial configuration device
*Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
*Support for 66- and 33-MHz, 64- and 32-bit PCI standard
*High-speed (640 Mbps) LVDS I/O support
*Low-speed (311 Mbps) LVDS I/O support
*311-Mbps RSDS I/O support
*Up to two PLLs per device provide clock multiplication and phase shifting
*Up to eight global clock lines with six clock resources available per logic array block (LAB) row
*Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM
*Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

EP1C4, EP1C6, EP1C12, EP1C20

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 The exciting ANT-2.45-CHP is of the one of the world’s smallest, high-performance 2.4 Ghz Chip Antennas.
It is ideal for all 2.4GHz applications including Bluetooth, 802.11, home RF, ZigBee and other popular and emerging standards.
The antenna uses an advanced multilayer LTCC Technology and a proprietary hybrid spiral
element to achieve size and performance characteristics superior to other designs.
The incredibly compact SMD package measures a mere 6.5mm (L) x 2.2mm (W) x 1.0mm (H) and is fully compatible with hand- and reflowattachment processes.
The antenna's favorable electrical specifications, stability and costeffectiveness make it the logical choice for a wide variety of applications.

* Incredibly Compact SMD Package
* Superior LTCC Technology
* 50Ω Characteristic Impedance
* Low Loss
* Wide Bandwidth
* Favorable Linear Polarization
* > Unity Gain
* No External Matching Required
* Highly Stable Over Temp. and Humidity
* Fully Hand- and Reflow-Assembly Compatible
* Cost-Effective

Any 2.4GHz Wireless Product Including:
* Bluetooth
* 802.11
* ZigBee
* Wireless PCMCIA Cards
* Telemetry
* Data Collection
* Industrial Process Monitoring
* Compact Wireless Products
* External Antenna Elimination

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General Description
ADD8608A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 8,392,608 words x 8 bits x 4 banks, Synchronous design allows precise cycle control the use of system clock I/O transactions are possible on every clock cycle. Data outputs occur at both rising edges of CK and CK.
 Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications.

•2.5V for VDDQ power supply
•SSTL_2 interface
•MRS Cycle with address key programs -CAS Latency (2, 2.5) -Burst Length (2,4 &8) -Burst Type (sequential & Interleave)
•4 banks operation
•Differential clock input (CK, /CK) operation
•Double data rate interface
•Auto & Self refresh
•8192 refresh cycle
•DQM for masking
•Package:66-pins 400 mil TSOP-Type II

TAG Bank, Data, SDRAM

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• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3,4,5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin

TAG bit, Data, DLL, DRAM, Rate, Strobe

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