GENERAL DESCRIPTION
The Micron® MT8LD864A X, MT16LD1664A X and MT32LD3264A X are randomly accessed 64MB, 128MB and 256MB memories organized in a x64 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely addressed through the 22/23 address bits, which are entered 12 bits (A0-A11) at RAS# time and 11/12 bits (A0-A11) at CAS# time.
READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READMODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location.

FEATURES
*Eight-CAS# ECC pinout in a 168-pin, dual in-line memory module (DIMM)
*64MB (8 Meg x 64), 128MB (16 Meg x 64), and 256MB (32 Meg x 64)
*Nonbuffered
*High-performance CMOS silicon-gate process
*Single +3.3V ±0.3V power supply
*All inputs, outputs and clocks are LVTTLcompatible
*4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms
*Extended Data-Out (EDO) PAGE MODE access cycle
*Serial presence-detect (SPD)

MT8LD864A, MT16LD1664A, MT8LD864AG-5X, MT16LD1664AG-5X, MT32LD3264AG-5X
TAG DRAM, Module

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DESCRIPTION
The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16.
HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
*Single 3.3±0.3V power supply
*All device pins are compatible with LVTTL interface
*JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by UDQM, LDQM
*Internal four banks operation
*Auto refresh and self refresh
*8192 refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or Full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks

HY57V121620T, HY57V121620LT, HY57V121620T-6, HY57V121620LT-6

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Description
The EM484M3244VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 1Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock.
The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL.
Available packages:TSOPII 86P 400mil.

Features
*Fully Synchronous to Positive Clock Edge
*Single 3.3V ±0.3V Power Supply
*LVTTL Compatible with Multiplexed Address
*Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page
*Programmable CAS Latency (C/L) - 2 or 3
*Data Mask (DQM) for Read / Write Masking
*Programmable Wrap Sequence
-Sequential (B/L = 1/2/4/8/full Page)
-Interleave (B/L = 1/2/4/8)
*Burst Read with Single-bit Write Operation
*All Inputs are Sampled at the Rising Edge of the System Clock
*Auto Refresh and Self Refresh
*4,096 Refresh Cycles / 64ms (15.625us)

EM484M3244VTA-75F, EM484M3244VTA-7F, EM484M3244VTA-6F

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General Description
The VDS7616A4A are four-bank Synchronous DRAMs organized as 2,097152 words x 16 bits x 4
banks.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system
applications

Features
*JEDEC standard LVTTL 3.3V power supply
*MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
*4 banks operation
*All inputs are sampled at the positive edge of the system clock
*Burst Read single write operation
*Auto & Self refresh
*4096 refresh cycle
*DQM for masking
*Package:54-pins 400 mil TSOP-Type II

VDS7616A4A-55, VDS7616A4A-6, VDS7616A4A-7

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Description
The HYB 39S512[40/80/16]0AT(L) are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4 banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 μm 512MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V ± 0.3 V power supply. All 512Mbit components are housed in P-TSOPII-54 packages.

Features
*Fully Synchronous to Positive Clock Edge
*0 to 70°C operating temperature
*Four Banks controlled by BA0 & BA1
*Programmable CAS Latency: 2 & 3
*Programmable Wrap Sequence: Sequential or Interleave
*Programmable Burst Length: 1, 2, 4, 8 and full page
*Multiple Burst Read with Single Write Operation
*Automatic and Controlled Precharge Command
*Data Mask for Read / Write control (×4, ×8)
*Data Mask for byte control (×16)
*Auto Refresh (CBR) and Self Refresh
*Power Down and Clock Suspend Mode
*8192 refresh cycles / 64 ms (7,8 μs)
*Random Column Address every CLK ( 1-N Rule)
*Single 3.3 V ± 0.3 V Power Supply
*LVTTL Interface versions
*Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16)

HYB 39S512400AT-7, HYB 39S512400AT-7.5, HYB 39S512400AT-8

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DESCRIPTION
The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32.
HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)

FEATURES
*Voltage : VDD, VDDQ 3.3V
*All device pins are compatible with LVTTL interface
*90Ball FBGA with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by DQM0,1,2 and 3
*Internal four banks operation
*Auto refresh and self refresh
*4096 Refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks
*Burst Read Single Write operation

HY5V52F-H, HY5V52F-P, HY5V52F-S, HY5V52FP-H, HY5V52FP-P

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GENERAL DESCRIPTION
The HSD8M32F4V/VA is a 8M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 120-pin, single-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M32F4V/VA is a SMM (Stackable Memory Module) designed and is intended for mounting into two 60-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
*Part Identification
-HSD8M32F4V : Height from bottom to top 11.3mm
-HSD8M32F4VA : Height from bottom to top 7.3mm
*Burst mode operation
*Auto & self refresh capability (4096 Cycles/64ms)
*LVTTL compatible inputs and outputs
*Single 3.3V ±0.3V power supply
*MRS cycle with address key programs
-Latency (Access from column address)
-Burst length (1, 2, 4, 8 & Full page)
-Data scramble (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*120pin SMM type FR4-PCB design
*The used device is 4Mx8bit x4Banks SDRAM
*Pin assignment is compatible with
-HSD16M64F8V/VA
-HSD32M64F8V/VA
-HSD8M64F8V/VA

HSD8M32F4VA, HSD8M32F4V-13, HSD8M32F4V-12, HSD8M32F4VA-13

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GENERAL DESCRIPTION
The KM416S1120D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG¢s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
*3.3V power supply
*LVTTL compatible with multiplexed address
*Dual banks operation
*MRS cycle with address key programs
-CAS Latency ( 2 & 3)
-Burst Length (1, 2, 4, 8 & full page)
-Burst Type (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*Burst Read Single-bit Write operation
*DQM for masking
*Auto & self refresh
*15.6us refresh duty cycle (2K/32ms)

KM416S1120DT-G/FC, KM416S1120DT-G/F6, KM416S1120DT-G/F7

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DESCRIPTION
The Hynix HY57V281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V281620HC(L)T is organized as 4banks of 2,097,152x16 HY57V281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
*Single 3.3±0.3V power supply
*All device pins are compatible with LVTTL interface
*JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
*All inputs and outputs referenced to positive edge of system clock
*Data mask function by UDQM or LDQM
*Internal four banks operation
*Auto refresh and self refresh
*4096 refresh cycles / 64ms
*Programmable Burst Length and Burst Type
-1, 2, 4, 8 or Full page for Sequential Burst
-1, 2, 4 or 8 for Interleave Burst
*Programmable CAS Latency ; 2, 3 Clocks

HY57V281620HCT-6, HY57V281620HCT-7, HY57V281620HCT-K, HY57V281620HCT-H

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GENERAL DESCRIPTION
The HSD16M72D18A is a 16M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy. Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M72D18A is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES
*Part Identification
-HSD16M72D18A-F/10L : 100MHz (CL=3)
-HSD16M72D18A-F/10 : 100MHz (CL=2)
-HSD16M72D18A-F/12 : 125MHz (CL=3)
-HSD16M72D18A-F/13 : 133MHz (CL=3)
-HSD16M72D18A-F/13H : 133MHz (CL=2)
-F means Auto & Self refresh with Low-Power (3.3V)
*Burst mode operation
*Auto & self refresh capability (4096 Cycles/64ms)
*LVTTL compatible inputs and outputs
*Single 3.3V ±0.3V power supply
*MRS cycle with address key programs
-Latency (Access from column address)
-Burst length (1, 2, 4, 8 & Full page)
-Data scramble (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock
*The used device is 8M x 8bit , 4Banks SDRAM

HSD16M72D18A-13, HSD16M72D18A-13H, HSD16M72D18A-12, HSD16M72D18A-10L

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