Description
The HB54A5129F1U is a 64M × 72 × 1 bank Double Data Rate (DDR) SDRAM Module, mounted 18 pieces of 256Mbits DDR SDRAM (HM5425401BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

Features
*184-pin socket type package (dual lead out)
-Outline: 133.35mm (Length) × 30.48mm (Height) × 4.00mm (Thickness)
-Lead pitch: 1.27mm
*2.5V power supply (VCC/VCCQ)
*SSTL-2 interface for all inputs and outputs
*Clock frequency: 143MHz/133MHz/125MHz (max.)
*Data inputs and outputs are synchronized with DQS
*4 banks can operate simultaneously and independently (Component)
*Burst read/write operation
*Programmable burst length: 2, 4, 8
-Burst read stop capability
*Programmable burst sequence
-Sequential
-Interleave
*Start addressing capability
-Even and Odd
*Programmable /CAS latency (CL): 3, 3.5
*8192 refresh cycles: 7.8μs (8192/64ms)
*2 variations of refresh
-Auto refresh
-Self refresh

HB54A5129F1U-A75B, HB54A5129F1U-B75B, HB54A5129F1U-10B

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Description
The EBE21RD4ABHA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM with sFBGA stacking technology. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each SDRAM on the module board.

Features
*240-pin socket type dual in line memory module (DIMM)
-PCB height: 30.0mm
-Lead pitch: 1.0mm
-Lead-free
*1.8V power supply
*Data rate: 533Mbps/400Mbps (max.)
*1.8 V (SSTL_18 compatible) I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in
capturing data at the receiver
*DQS is edge aligned with data for READs; center aligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data referenced to both edges of DQS
*Four internal banks for concurrent operation (Components)
*Burst length: 4, 8
*/CAS latency (CL): 3, 4, 5
*Auto precharge option for each burst access
*Auto refresh and self refresh modes
*7.8μs average periodic refresh interval
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation
*1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)

EBE21RD4ABHA-5C-E, EBE21RD4ABHA-4A-E

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Description
The EBE51UD8AEFA is 64M words × 64 bits, 1 rank DDR2 SDRAM unbuffered module, mounting 8 pieces of 512M bits DDR2 SDRAM sealed in FBGA (μBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4 bits prefetchpipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (μBGA) on the module board.

Features
*240-pin socket type dual in line memory module (DIMM)
- PCB height: 30.0mm
- Lead pitch: 1.0mm
- Lead-free
*Power supply: VDD = 1.8V ± 0.1V
*Data rate: 667Mbps (max.)
*SSTL_18 compatible I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used capturing data at the receiver
*DQS is edge aligned with data for READs: centeraligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS
*Four internal banks for concurrent operation (components)
*Data mask (DM) for write data
*Burst lengths: 4, 8
*/CAS Latency (CL): 3, 4, 5
*Auto precharge operation for each burst access
*Auto refresh and self refresh modes
*Average refresh period
- 7.8μs at 0°C ≤ TC ≤ +85°C
- 3.9μs at +85°C < TC ≤ +95°C
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation

EBE51UD8AEFA-6E-E
TAG DIMM, SDRAM

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Features
* 200-pin, small-outline, dual in-line memory module (SODIMM)
* Fast data transfer rates: PC1600, PC2100, and PC2700
* Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR SDRAM components
* 512MB (64 Meg x 64), 1GB (128 Meg x 64)
* VDD = VDDQ = +2.5V
* VDDSPD = +2.3V to +3.6V
* 2.5V I/O (SSTL_2 compatible)
* Commands entered on each positive CK edge
* DQS edge-aligned with data for READs; centeraligned with data for WRITEs
* Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
* Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data capture
* Differential clock inputs CK and CK#
* Four internal device banks for concurrent operation
* Programmable burst lengths: 2, 4, or 8
* Auto precharge option
* Auto Refresh and Self Refresh Modes
* 7.8125μs maximum average periodic refresh interval
* Serial Presence Detect (SPD) with EEPROM
* Programmable READ CAS latency
* Gold edge contacts

MT16VDDF6464H
MT16VDDF12864H

TAG DDR, DIMM, SDRAM

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DESCRIPTION
 The MPMB62D-68KX3 is 32M bit x 64 Double Data Rate Synchronous Dynamic RAM high density memory module based on 128Mb DDR SDRAM respectively.
The MPMB62D-68KX3 consists of sixteen CMOS 16M ´ 8 bit with 4 banks Double Data Rate Synchronous DRAMs in TinyBGA package and a 2K EEPROM in 8-Pin TSSOP package mounted on a 184pin glass-epoxy substrate.
Two 0.1μF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM.
The MPMB62D-68KX3 is a Dual In-line Memory Module and is intended for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock.
Data I/O transactions are possible on both edges of every clock cycle.
Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
* Performance range - 166MHz ( DDR333, CL2.5 )
* Double-data-rate architecture; two data transfers per clock cycle
* Bi-directional data strobe (DQS)
* Differential clock inputs (CK and /CK)
* DLL aligns DQ and DQS transition with CK transition
* Auto & self refresh capability (4096 Cycles / 64ms)
* Single 2.5V ±0.2V power supply
* Programmable Read latency 2, 2.5 (clock)
* Programmable Burst length (2, 4, 8)
* Programmable Burst type (Sequential & Interleave)
* Edge aligned data output, center aligned data input
* Serial presence detect with EEPROM
* PCB : Height (1,181 mil), double sided component

TAG DDR, DIMM, SDRAM, SPD

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Specifications
* Density: 512MB
* Organization
- 64M words × 72 bits, 1 rank
* Mounting 9 pieces of 512M bits DDR2 SDRAM sealed in FBGA
* Package
- 240-pin fully buffered, socket type dual in line memory module (FB-DIMM)
  PCB height: 30.35mm
  Lead pitch: 1.00mm
- Advanced Memory Buffer (AMB): 655-ball FCBGA
- Lead-free (RoHS compliant)
* Power supply
- DDR2 SDRAM: VDD = 1.8V ± 0.1V
- AMB: VCC = 1.5V + 0.075V/−0.045
* Data rate: 667Mbps/533Mbps (max.)
* Four internal banks for concurrent operation (components)
* Interface: SSTL_18
* Burst lengths (BL): 4, 8
* /CAS Latency (CL): 3, 4, 5
* Precharge: auto precharge option for each burst access
* Refresh: auto-refresh, self-refresh
* Refresh cycles: 8192 cycles/64ms
- Average refresh period
  7.8μs at 0°C ≤ TC ≤ +85°C
  3.9μs at +85°C < TC ≤ +95°C
* Operating case temperature range
- TC = 0°C to +95°C

Features
* JEDEC standard Raw Card A Design
* Industry Standard Advanced Memory Buffer (AMB)
* High-speed differential point-to-point link interface at 1.5V (JEDEC draft spec)
- 14 north-bound (NB) high speed serial lanes
- 10 south-bound (SB) high speed serial lanes
* Various features/modes:
- MemBIST and IBIST test functions
- Transparent mode and direct access mode for DRAM testing
- Interface for a thermal sensor and status indicator
* Channel error detection and reporting
* Automatic DDR2 SDRAM bus and channel calibration
* SPD (serial presence detect) with 1piece of 256 byte serial EEPROM

EBE51FD8AGFD-6E-E
EBE51FD8AGFD-5C-E
EBE51FD8AGFN-6E-E
EBE51FD8AGFN-5C-E

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