General Description
The XPIO™ 110GXS is a fully integrated 10 Gbps serializer/deserializer device designed for high-speed switches and routers that require very low power budget and a small footprint as well. Centering on 10 Gbps speed, the XPIO 110GXS is a versatile chip that is capable of handling applications in various standards, such as OC-192 (9.95 Gbps) and 10GE (10.31 Gbps).
An on-chip low jitter PLL generates all required clocks based on an external reference clock at 1/16 or 1/64 frequency of the serial data rate, which is 622.08 MHz or 155.52 MHz, respectively, for OC-192 applications. An Integrated Limiting Amplifier allows flexibility in placement and reduced bit-error rates (BER).
Fabricated with state-of-the-art CMOS technology, the XPIO 110GXS performs all necessary functions for serial-to-parallel and parallel-to-serial conversions, and consumes less than one third of the power consumed by the more conventional SiGe Bi-CMOS designs.

*Single chip SERDES solution with integrated transmitter and receiver
*Continuous serial operation range from 9.95 Gbps to 10.31 Gbps
*Parallel LVDS data range from 622 Mbps to 644 Mbps
*Low power consumption (800 mW typical)
*Performs 16:1 serialization and 1:16 deserialization
*Embedded Limiting Amplifier enhances receiver sensitivity
*Low-jitter PLL for clock generation
*On-chip Clock Data Recovery circuit
*On-chip FIFO to decouple transmit clocks
*Bit order swap for 10GE operations
*Programmable 4-phase LVDS clock output for easy system design
*Repeating serial data output
*Line loopback, diagnostic loopback, and simultaneous loopback modes
*Frequency Lock Alarm Output
*Programmable differential output swing on both Serial driver and Parallel LVDS driver
*1.3V core voltage and 2.5V I/O voltage
*Supports 10GE (10-Gigabit Ethernet), OC-192, XFP, XSBI and SFI-4.1 interfaces
*269-pin flip-chip BGA (15 x 15 mm body size, 0.8 mm pitch)
*-40 to 85°C operating temperature

LS110GXS-1CF269C, LS110GXS-2CF269C, LS110GXS-1CF269I

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The GS9090B is a 270Mb/s reclocking deserializer with an internal FIFO.
It provides a complete receive solution for SD-SDI and DVB-ASI applications.
In addition to reclocking and deserializing the input data stream, the GS9090B performs NRZI-to-NRZ decoding, descrambling as per SMPTE 259M-C, and word alignment when operating in SMPTE mode.
When operating in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream.
The internal reclocker features a very wide input jitter tolerance, and is fully compatible with both SMPTE and DVB-ASI input streams.
The GS9090B includes a range of data processing functions such as EDH support (error detection and handling), and automatic standards detection.
The device can also detect and extract SMPTE 352M payload identifier packets and independently identify the received video standard.
 This information is read from internal registers via the host interface port.
The GS9090B also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, MPEG packet extraction and clock rate interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed format, with the associated parallel clock output signal operating at 27MHz.
The device may also be used in a low-latency data pass through mode where only descrambling and word alignment will be performed in SMPTE mode.

Key Features
* SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding (with bypass)
* DVB-ASI sync word detection and 8b/10b decoding
* Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI
data packet extraction and clock rate interchange, and ancillary data packet extraction
* Integrated VCO and reclocker
* Automatic or manual selection between SMPTE video and DVB-ASI data
* User selectable additional processing features including:
* TRS, ANC data checksum, and EDH CRC error detection and correction
* programmable ANC data detection
* illegal code remapping
* Internal flywheel for noise immune H, V, F extraction
* Automatic standards detection and indication
* Enhanced Gennum Serial Peripheral Interface (GSPI)
* JTAG test interface
* Polarity insensitive for DVB-ASI and SMPTE signals
* +1.8V core power supply with optional +1.8V or +3.3V I/O power supply
* Small footprint (8mm x 8mm)
* Low power operation (typically 145mW)
* Pb-free

* SMPTE 259M-C Serial Digital Interfaces
* DVB-ASI Serial Digital Interfaces

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