FUNCTIONAL DESCRIPTION
The DLO31F-series device is a gated delay line oscillator. The device produces a stable square wave which is synchronized with the falling edge of the Gate Input (GB). The frequency of oscillation is given by the device dash number (See Table). The two outputs (C1,C2) are in phase during oscillation, but return to opposite logic levels when the device is disabled.

FEATURES
*Continuous or keyable wave train
*Synchronizes with arbitrary gating signal
*Fits standard 14-pin DIP socket
*Low profile
*Auto-insertable
*Input & outputs fully TTL interfaced & buffered
*Available in frequencies from 2MHz to 40MHz

DLO31F-2, DLO31F-2.5, DLO31F-3, DLO31F-3.5, DLO31F-4, DLO31F-4.5

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FUNCTIONAL DESCRIPTION
The 3D7418 Programmable 8-Bit Silicon Delay Line product family consists of 8-bit, user-programmable CMOS silicon integrated circuits. Delay values, programmed either via the serial or parallel interface, can be varied over 255 equal steps ranging from 250ps to 5.0ns inclusively. Units have a typical inherent (zero step) delay of 12ns to 17ns (See Table 1). The input is reproduced at the output without inversion, shifted in time as per user selection.
The 3D7418 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7418 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Increment range: 0.25 through 5.0ns
*Delay tolerance: 1% (See Table 1)
*Temperature stability: ±3% typical (0C-70C)
*Vdd stability: ±1% typical (4.75V-5.25V)
*Minimum input pulse width: 10% of total delay
*Programmable via 3-wire serial or 8-bit parallel interface

3D7418-0.25, 3D7418-0.5, 3D7418-1, 3D7418-2, 3D7418-3, 3D7418-4, 3D7418-5

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FUNCTIONAL DESCRIPTION
The 1518-series device is a fixed, single-input, fiveoutput, passive delay line. The signal input (IN) is reproduced at the outputs (T1-T5) in equal increments. The delay from IN to T5 (TD) and the characteristic impedance of the line (Z) are determined by the dash number. The rise time (TR) of the line is 30% of TD, and the 3dB bandwidth is given by 1.05 / TD. The device is available in a 14-pin SMD with two pinout options.
Part numbers are constructed according to the scheme shown at right. For example, 1518-101-500A is a 100ns, 50W delay line with pinout code A. Similarly, 1518-151-501 a is 150ns, 500W delay line with standard pinout.

FEATURES
*5 taps of equal delay increment
*Delays to 200ns
*Low profile
*Epoxy encapsulated
*Meets or exceeds MIL-D-23859C

1518-5-10IN, 1518-10-10IN, 1518-15-10IN, 1518-100-10IN, 1518-200-10IN
TAG DELAY, line, SMD

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FUNCTIONAL DESCRIPTION
The 3D3424 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. For each line, the delay time is given by:
TDn = T0 + An * TI
where T0 is the inherent delay, An is the delay address of the n-th line and TI is the delay increment (dash number). The desired addresses are shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The serial interface can also be used to enable/disable each delay line. The 3D3424 operates at 3.3 volts and has a typical T0 of 9ns. The 3D3424 is CMOS-compatible, capable of sourcing or sinking 4mA loads, and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC.

FEATURES
*Four indep’t programmable lines on a single chip
*All-silicon CMOS technology
*Low quiescent current (5mA typical)
*Leading- and trailing-edge accuracy
*Vapor phase, IR and wave solderable
*Increment range: 1ns through 300ns
*Delay tolerance: 3% or 2ns (see Table 1)
*Line-to-line matching: 1% or 1ns typical
*Temperature stability: ±1.5% typical (-40C to 85C)
*Vdd stability: ±0.5% typical (3.0V to 3.6V)
*Minimum input pulse width: 10% of total delay

3D3424-1, 3D3424-1.5, 3D3424-2, 3D3424-4, 3D3424-5, 3D3424-10, 3D3424-15
3D3424-20, 3D3424-40, 3D3424-50, 3D3424-100, 3D3424-200, 3D3424-300

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FUNCTIONAL DESCRIPTION
The 3D7323 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains three matched, independent delay lines. Delay values can range from 6ns through 6000ns. The input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. The 3D7323 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7323 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Delay range: 6 through 6000ns
*Delay tolerance: 2% or 1.0ns
*Temperature stability: ±3% typ (-40C to 85C)
*Vdd stability: ±1% typical (4.75V to 5.25V)
* Minimum input pulse width: 20% of total delay
*14-pin DIP available as drop-in replacement for hybrid delay lines

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General Description
The ICS1523 is a low-cost, high-performance frequency generator. It is well suited to general
purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using IDT’s advanced low-voltage CMOS mixed-mode technology, the ICS1523 is an effective phase controlled clock synthesizer and also supports video projectors and displays at resolutions from VGA to beyond UXGA.
The ICS1523 offers clock outputs in both differential to 250 MHz) and single-ended (to 150 MHz) formats.
Dynamic Phase Adjust (DPA) allows I2C™ control of the output clock’s phase relative to the input sync signal. A second, half speed set of outputs that can be separately enabled allows such applications as clocking analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output, or the input HSYNC after being sharpened by the Schmitt trigger. Both signals are then delayed by the DPA.
The advanced PLL uses either its internal programmable feedback divider or an external divider.
Either the internal or external loop filters is software selectable. The COAST input pin disables the PLL’s charge pump, causing the device to idle at the current speed for short periods of time, such as vertical blanking intervals.
The device is programmed by a standard I2C-bus serial interface and is available in a 24-pin, wide small-outline integrated circuit (SOIC) package.

Features
• Low Jitter
• Wide input frequency range
• 15.734 kHz to 100 MHz
• PECL differential outputs
• Up to 250 MHz
• SSTL_3 Single-ended clock outputs
• Up to 150 MHz
• Dynamic Phase Adjust (DPA) for all outputs
• I2C controlled phase adjustment
• Full clock cycle down to 1/64 of a clock
• Double-buffered control registers
• External or internal loop filter selection
• COAST input can disable charge pump
• 3.3 VDD
• 5 volt Tolerant Inputs
• Industry Standard I2C-bus programming interface
• PLL Lock detection via I2C or LOCK/REF output pin
• 24-pin 300-mil SOIC package
• Available in Pb-free packaging

Applications
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems

ICS1523M
ICS1523MT
ICS1523MLF
ICS1523MLFT

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Application
In TV sets, the integrated baseband delay line circuit is suitable for decoders with color-difference signal outputs

Description
The integrated delay line circuit U3661M is suitable for all chroma decoders with baseband color-difference outputs. It is suitable for PAL-, SECAM- and NTSC-signals as well. The U3661M contains two separate delay lines for processing (R–Y)-output and (B–Y)-output separately. The delay is performed by internally switched capacitors. On-chip postfiltering
avoids the need for external filter components.
A summing circuitry combines the information of adjacent TV-lines, thus giving an interpolated sum for the PAL-system, storing preceeding lines for the SECAMsystem and providing a comb-filtered output for NTSC-signals. Due to internally-generated timing, synchronization is easily done by feeding a line-frequent impulse (usually the SC-impulse) to the sync-input of the IC.

Features
* One line delay time, addition of delayed and non-delayed output signals
* Adjustment-free application, VCO without external components
* Handles negative or positive color-difference input signals
* Clamping of ac-coupled input signals [±(R–Y) and ±(B–Y)]
* Line-locked by the sandcastle pulse
* No crosstalk between SECAM color carriers (diaphoty)
* Comb filtering functions for NTSC color-difference signals
* Correction of phase errors in the PAL system

U3661M-ADP
U3661M-AFP

TAG DELAY

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The NCV8675 is a precision 5.0 V and 3.3 V fixed output, low dropout integrated voltage regulator with an output current capability of 350 mA. Careful management of light load current consumption, combined with a low leakage process, achieve a typical quiescent ground current of 34 uA.
NCV8675 is pin for pin compatible with NCV4275 and it could replace this part when very low quiescent current is required.
The output voltage is accurate within ±2.0%, and maximum dropout voltage is 600 mV at full rated load current.
It is internally protected against input transients, input supply reversal, output overcurrent faults, and excess die temperature. No external components are required to enable these features.

Features
* 5 V and 3.3 V Fixed Output (2.5 V Version Available Upon Request)
* ±2.0% Output Accuracy, Over Full Temperature Range
* 34 uA Typical Quiescent Current at IOUT = 100 uA, 50 uA Maximum up to 85°C
* 600 mV Maximum Dropout Voltage at 350 mA Load Current
* Wide Input Voltage Operating Range of 5.5 V to 45 V
* Internal Fault Protection
+ -42 V Reverse Voltage
+ Short Circuit/Overcurrent
+ Thermal Overload
* AEC-Q100 Qualified
* EMC Compliant
* NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes
* These are Pb-Free Devices

NCV8675DS50G
NCV8675DS50R4G
NCV8675DS33G
NCV8675DS33R4G

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FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 0.75ns through 7000ns
• Delay tolerance: 2% or 0.5ns
• Temperature stability: ±2% typical (-40C to 85C)
• Vdd stability: ±1% typical (3.0V-3.6V)
• Minimum input pulse width: 15% of total delay
• 14-pin Gull-Wing available as drop-in replacement for hybrid delay lines

FUNCTIONAL DESCRIPTION
 The 3D3220 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 700ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number.
 
 The 3D3220 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy. The all-CMOS 3D3220 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14-pin SOIC and 16-pin SOL packages.

APPLICATION NOTES
OPERATIONAL DESCRIPTION The 3D3220 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

OPERATING FREQUENCY
The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

 To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D3220 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH
 The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

 To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D3220 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

3D3220-xx
3D3220G-XX
3D3220D-xx
3D3220S-xx

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