Description
The EBE21RD4ABHA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM with sFBGA stacking technology. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each SDRAM on the module board.

Features
*240-pin socket type dual in line memory module (DIMM)
-PCB height: 30.0mm
-Lead pitch: 1.0mm
-Lead-free
*1.8V power supply
*Data rate: 533Mbps/400Mbps (max.)
*1.8 V (SSTL_18 compatible) I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in
capturing data at the receiver
*DQS is edge aligned with data for READs; center aligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data referenced to both edges of DQS
*Four internal banks for concurrent operation (Components)
*Burst length: 4, 8
*/CAS latency (CL): 3, 4, 5
*Auto precharge option for each burst access
*Auto refresh and self refresh modes
*7.8μs average periodic refresh interval
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation
*1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)

EBE21RD4ABHA-5C-E, EBE21RD4ABHA-4A-E

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Specifications
* Density: 1GB
* Organization
- 128M words × 72 bits, 1 rank
* Mounting 18 pieces of 512M bits DDR2 SDRAM sealed in FBGA
* Package: 240-pin socket type dual in line memory module (DIMM)
- PCB height: 30.0mm
- Lead pitch: 1.0mm
- Lead-free (RoHS compliant)
* Power supply: VDD = 1.8V ± 0.1V
* Data rate: 667Mbps/533Mbps/400Mbps (max.)
* Four internal banks for concurrent operation (components)
* Interface: SSTL_18
* Burst lengths (BL): 4, 8
* /CAS Latency (CL): 3, 4, 5
* Precharge: auto precharge option for each burst access
* Refresh: auto-refresh, self-refresh
* Refresh cycles: 8192 cycles/64ms
- Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
* Operating case temperature range
- TC = 0°C to +95°C

Features
* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
* DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
* Differential clock inputs (CK and /CK)
* DLL aligns DQ and DQS transitions with CK transitions
* Commands entered on each positive CK edge; data referenced to both edges of DQS
* Posted /CAS by programmable additive latency for better command and data bus efficiency
* Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality
* /DQS can be disabled for single-ended Data Strobe operation
* 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2K bits EEPROM) for Presence Detect (PD)

EBE10RD4AJFA-6E-E
EBE10RD4AJFA-5C-E
EBE10RD4AJFA-4A-E

TAG 1GB, DDR2, SDRAM

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Specifications
• Density: 512M bits
• Organization
 32M words × 4 bits × 4 banks (EDE5104AJSE)
 16M words × 8 bits × 4 banks (EDE5108AJSE)
 8M words × 16 bits × 4 banks (EDE5116AJSE)
• Package
 60-ball FBGA (EDE5104/08AJSE)
 84-ball FBGA (EDE5116AJSE)
 Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• 1KB page size
 Row address: A0 to A13
 Column address: A0 to A9, A11 (EDE5104AJSE) A0 to A9 (EDE5108AJSE)
• 2KB page size (EDE5116AJSE)
 Row address: A0 to A12
 Column address: A0 to A9
• Four internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
 Sequential (4, 8)
 Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
 Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
 TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation

EDE5108AJSE
EDE5116AJSE
TAG DDR2, SDRAM

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Specifications
• Density: 2G bits
• Organization
- 64M words × 4 bits × 8 banks (EDE2104ABSE)
-  32M words × 8 bits × 8 banks (EDE2108ABSE)
• Package
- 68-ball FBGA
- Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate
- 800Mbps/667Mbps/533Mbps (max.)
• 1KB page size
- Row address: A0 to A14
- Column address: A0 to A9, A11 (EDE2104ABSE) A0 to A9 (EDE2108ABSE)
• Eight internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
- Sequential (4, 8)
- Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
- Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
- TC = 0°C to +95°C

Features
• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation

EDE2108ABSE
TAG DDR2, SDRAM

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1.1.1 Key Features
• VDD = 1.8V +/- 0.1V
• VDDQ = 1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• 8 banks
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal eight bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) , 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry

HY5PS1G431C(L)FP-XX*
HY5PS1G831C(L)FP-XX*
HY5PS1G1631C(L)FP-XX*
TAG DDR2, SDRAM

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Description
• VDD=1.8V
• VDDQ=1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe suupported (x8 only)
• Self-Refresh High Temperature Entry
• Lead Free Package

HY5PS12421FP
HY5PS12821FP
HY5PS121621FP
HY5PS12421FP-X
HY5PS12821FP-X
HY5PS121621FP-X
TAG DDR2, SDRAM

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