'DDR SDRAM' related articles 2

  1. 2009/06/05 HB54A5129F1U - 512MB Registered DDR SDRAM DIMM
  2. 2008/04/03 HY5DU56422CT - 256M-P DDR SDRAM
The HB54A5129F1U is a 64M × 72 × 1 bank Double Data Rate (DDR) SDRAM Module, mounted 18 pieces of 256Mbits DDR SDRAM (HM5425401BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

*184-pin socket type package (dual lead out)
-Outline: 133.35mm (Length) × 30.48mm (Height) × 4.00mm (Thickness)
-Lead pitch: 1.27mm
*2.5V power supply (VCC/VCCQ)
*SSTL-2 interface for all inputs and outputs
*Clock frequency: 143MHz/133MHz/125MHz (max.)
*Data inputs and outputs are synchronized with DQS
*4 banks can operate simultaneously and independently (Component)
*Burst read/write operation
*Programmable burst length: 2, 4, 8
-Burst read stop capability
*Programmable burst sequence
*Start addressing capability
-Even and Odd
*Programmable /CAS latency (CL): 3, 3.5
*8192 refresh cycles: 7.8μs (8192/64ms)
*2 variations of refresh
-Auto refresh
-Self refresh

HB54A5129F1U-A75B, HB54A5129F1U-B75B, HB54A5129F1U-10B

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 The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.

• VDD/VDDQ = 2.5 ~ 2.7V
• All inputs and outputs are compatible with SSTL_2 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
• On chip DLL align DQ and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• CAS latency 3 supported
• Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
• Internal four bank operations with single pulsed /RAS
• tRAS Lock-out function supported
• Auto refresh and Self refresh supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Full and Half strength driver option controlled by EMRS


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