General Description
The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quadbank DRAM.
The 1Gb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 1Gb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte.
The 1Gb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatible.

Features
*VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
*Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
*Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
*Differential clock inputs (CK and CK#)
*Commands entered on each positive CK edge
*DQS edge-aligned with data for READs; centeraligned with data for WRITEs
*DLL to align DQ and DQS transitions with CK
*Four internal banks for concurrent operation
*Data mask (DM) for masking write data (x16 has two–one per byte)
*Programmable burst lengths: 2, 4, or 8
*Auto Refresh and Self Refresh Modes
*Longer lead TSOP for improved reliability (OCPL)
*2.5V I/O (SSTL_2 compatible)
*Concurrent auto precharge option is supported
*tRAS lockout supported (tRAP = tRCD)

MT46V128M8, MT46V64M16
TAG DDR, SDRAM

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DESCRIPTION
The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination.
The UTC UR5596 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. Besides, an active low shutdown (SHDN) pin provides Suspend To RAM (STR) functionality. When SHDN is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
Regarding the output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ/2. The output stage has been designed to maintain excellent load
regulation while preventing shoot through. The UTC UR5596 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation and permits UTC UR5596 to provide a termination solution for DDRII SDRAM.

FEATURES
*Source and sink current
*Low output voltage offset
*No external resistors required
*Linear topology
*Suspend To Ram (STR) functionality
*Low external component count
*Thermal shutdown protection

UR5596-S08-R, UR5596L-S08-R, UR5596-S08-T, UR5596L-S08-T

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Description
The 34716 is a highly integrated, space-efficient, low cost, dual synchronous buck switching regulator with integrated N-channel power MOSFETs. It is a high performance point-of-load (PoL) power supply with its second output having the ability to track an external reference voltage. it provides a full power supply solution for Double-Data-Rate (DDR) Memories.
Channel one provides a source only, 5.0 A drive capability, while channel two can sink and source up to 3.0 A. Both channels are highly efficient with tight output regulation. With its high current drive capability, channel one can be used to supply the VDDQ to the memory chipset. The second channel’s ability to track a reference voltage makes it ideal to provide the termination voltage (VTT) for modern data buses. The 34716 also provides a buffered output reference voltage (VREFOUT) to the memory chipset The 34716 offers the designer the flexibility of many control, supervisory, and protection functions to allow for easy implementation of complex designs. It is housed in a Pb-free, thermally enhanced, and space efficient 26-Pin Exposed Pad QFN.

Features
*50 mΩ integrated N-channel power MOSFETs
*Input voltage operating range from 3.0 to 6.0 V
*±1% accurate output voltages, ranging from 0.7 to 3.6 V
*The second output tracks 1/2 an external reference voltage
*±1% accurate buffered reference output voltage
*Programmable switching frequency range from 200 kHz to 1.0 MHz
*Programmable soft start timing for channel one
*Over-current limit and short-circuit protection on both channels
*Thermal shutdown
*Output over-voltage and under-voltage detection
*Active low power good output signal
*Active low standby and shutdown inputs
*Pb-free packaging designated by suffix code EP.

MC34716EP/R2

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Specifications
*Density: 512M bits
*Organization
- 16M words × 8 bits × 4 banks (EDD5108AGTA)
- 8M words × 16 bits × 4 banks (EDD5116AGTA)
*Package: 66-pin plastic TSOP (II)
- Lead-free (RoHS compliant)
*Power supply: VDD, VDDQ = 2.5V ± 0.2V
*Data rate: 400Mbps/333Mbps/266Mbps (max.)
*Four internal banks for concurrent operation
*Interface: SSTL_2
*Burst lengths (BL): 2, 4, 8
*Burst type (BT):
- Sequential (2, 4, 8)
- Interleave (2, 4, 8)
*/CAS Latency (CL): 2, 2.5, 3
*Precharge: auto precharge option for each burst access
*Driver strength: normal/weak
*Refresh: auto-refresh, self-refresh
*Refresh cycles: 8192 cycles/64ms
- Average refresh period: 7.8μs
*Operating ambient temperature range
- TA = 0°C to +70°C

Features
*Double-data-rate architecture; two data transfers per clock cycle
*The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
*Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
*Data inputs, outputs, and DM are synchronized with DQS
*DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
*Data mask (DM) for write data

DDR400B, DDR400C, DDR333B, DDR266A, DDR266B
TAG DDR, SDRAM

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Features
* 200-pin, small-outline, dual in-line memory module (SODIMM)
* Fast data transfer rates: PC1600, PC2100, and PC2700
* Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR SDRAM components
* 512MB (64 Meg x 64), 1GB (128 Meg x 64)
* VDD = VDDQ = +2.5V
* VDDSPD = +2.3V to +3.6V
* 2.5V I/O (SSTL_2 compatible)
* Commands entered on each positive CK edge
* DQS edge-aligned with data for READs; centeraligned with data for WRITEs
* Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
* Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data capture
* Differential clock inputs CK and CK#
* Four internal device banks for concurrent operation
* Programmable burst lengths: 2, 4, or 8
* Auto precharge option
* Auto Refresh and Self Refresh Modes
* 7.8125μs maximum average periodic refresh interval
* Serial Presence Detect (SPD) with EEPROM
* Programmable READ CAS latency
* Gold edge contacts

MT16VDDF6464H
MT16VDDF12864H

TAG DDR, DIMM, SDRAM

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DESCRIPTION
 The MPMB62D-68KX3 is 32M bit x 64 Double Data Rate Synchronous Dynamic RAM high density memory module based on 128Mb DDR SDRAM respectively.
The MPMB62D-68KX3 consists of sixteen CMOS 16M ´ 8 bit with 4 banks Double Data Rate Synchronous DRAMs in TinyBGA package and a 2K EEPROM in 8-Pin TSSOP package mounted on a 184pin glass-epoxy substrate.
Two 0.1μF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM.
The MPMB62D-68KX3 is a Dual In-line Memory Module and is intended for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock.
Data I/O transactions are possible on both edges of every clock cycle.
Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
* Performance range - 166MHz ( DDR333, CL2.5 )
* Double-data-rate architecture; two data transfers per clock cycle
* Bi-directional data strobe (DQS)
* Differential clock inputs (CK and /CK)
* DLL aligns DQ and DQS transition with CK transition
* Auto & self refresh capability (4096 Cycles / 64ms)
* Single 2.5V ±0.2V power supply
* Programmable Read latency 2, 2.5 (clock)
* Programmable Burst length (2, 4, 8)
* Programmable Burst type (Sequential & Interleave)
* Edge aligned data output, center aligned data input
* Serial presence detect with EEPROM
* PCB : Height (1,181 mil), double sided component

TAG DDR, DIMM, SDRAM, SPD

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FEATURES
· Maximum Sample Rate: 125 MSPS
· 14-Bit Resolution with No Missing Codes
· 3.5 dB Coarse Gain and up to 6 dB TPrraodgera-Omfmf able Fine Gain for SNR/SFDR
· Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
· Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400
mVPP
· Clock Duty Cycle Stabilizer
· Internal Reference with Support for External Reference
· No External Decoupling Required for References
· Programmable Output Clock Position and Drive Strength to Ease Data Capture
· 3.3-V Analog and 1.8-V to 3.3-V Digital Supply
· 32-QFN Package (5 mm ´ 5 mm)
· Pin Compatible 12-Bit Family (ADS612X)

APPLICATIONS
· Wireless Communications Infrastructure
· Software Defined Radio
· Power Amplifier Linearization
· 802.16d/e
· Test and Measurement Instrumentation
· High Definition Video
· Medical Imaging

ADS6142IRHBR
ADS6142IRHBRG4
ADS6142IRHBT

TAG CMOS, DDR, Outputs

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Specifications
• Density: 256M bits
• Organization
-8M words × 8 bits × 4 banks (EDD2508AETA)
-4M words × 16 bits × 4 banks (EDD2516AETA)
• Package: 66-pin plastic TSOP (II)
- Lead-free (RoHS compliant)
• Power supply:
-DDR400: VDD, VDDQ = 2.6V ± 0.1V
-DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 400Mbps/333Mbps/266Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
-Sequential (2, 4, 8)
-Interleave (2, 4, 8)
• /CAS Latency (CL): 2, 2.5, 3
• Precharge: auto precharge option for each burst access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
-Average refresh period: 7.8μs
• Operating ambient temperature range
-TA = 0°C to +70°C

Features
• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with DQS
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data

EDD2516AETA
EDD2508AETA-5B-E
EDD2508AETA-5C-E
EDD2508AETA-6B-E
EDD2508AETA-7A-E
EDD2508AETA-7B-E
EDD2516AETA-5B-E
EDD2516AETA-5C-E
EDD2516AETA-6B-E
EDD2516AETA-7A-E
EDD2516AETA-7B-E
TAG DDR, SDRAM

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Features
* VCNTL Supply Voltage: 3.3V to 5.5V
* Termination Supply Voltage: 1.8V to 3.6V
* Support Both DDR I(1.25VTT) and DDR II (0.9 VTT) Requirements
* Requires Only 20μF Ceramic Output Capacitor
* Low Output Offset
* 3A Source and Sink Current
* Low External Component Count
* No Inductor Required
* Thermal Shutdown Protection
* Over Current Protection
* Suspend to RAM (STR) Function with High-impedance output
* SOP-8 (FD) Package

Applications
* DDR-SDRAM Termination Voltage
* DDR I / DDR II Termination Voltage
* SSTL-18
* SSTL-2
* SSTL-3

General Description
The G2992 is a linear regulator designed to meet the JEDEC SSTL-18, SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR I / II -SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This device can deliver 3A continuous current in the application such as required for DDR I/ II SDRAM termination. The G2992 can easily provide the accurate VTT voltage with two external resistors generating reference voltage. The quiescent current is as low as 750μA @ VCNTL = 3.3V. So the power consumption can meet the low power consumption applications.
The G2992 also has a shutdown function by setting VREF smaller than 0.2V, that provides Suspend to RAM (STR) functionality. When in the shutdown mode, the VTT output (on VOUT pin) will be tri-state providing a high impendence. A power saving advantage can be obtained in this mode through lowering the quiescent current to 50μA @ VCNTL = 3.3V.

G2992F1U

TAG DDR, Regulator

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FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future frequency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus.
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock rising edges only.
• Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data traceability.
• Single address bus.
• Byte write function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 15x17mm & Lead Free

GENERAL DESCRIPTION
 The K7I643684M and K7I641884M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for K7I643684M and 4,194,304 words by 18 bits for K7I641884M.

 Address, data inputs, and all control signals are synchronized to the input clock (K or K).
Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K).
Read data are referenced to echo clock (CQ or CQ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fixed to 4-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.

 Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins for x18 (x36) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

 The K7I643684M and K7I641884M are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.


K7I641884M
K7I643684M-F(E)C(I)30
K7I643684M-F(E)C(I)25
K7I643684M-FC(I)20
K7I643684M-FC(I)16
K7I641884M-F(E)C(I)30
K7I641884M-F(E)C(I)25
K7I641884M-FC(I)20
K7I641884M-FC(I)16

TAG DDR, SRAM

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