'D Flip-Flop' related articles 1

  1. 2008/07/23 AZ10E131 - ECL/PECL 4-bit D Flip-Flop
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs.
Each flip-flop may be locked separately by holding Common Clock (CC) LOW and using the Clock Enable (C¯¯En) inputs for clocking.
Common clocking is achieved by holding the C¯¯En inputs LOW and using CC to clock all four flip-flops.
In this case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn).
Asynchronous set controls (Sn) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both CC and C¯¯En are LOW, and transfers to the slave when either CC or C¯¯En (or both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

* 1100 MHz Min. Toggle Frequency
* Differential Outputs
* Individual and Common Clocks
* Individual Resets (asynchronous)
* Paired Sets (asynchronous)
* Operating Range of 4.2V to 5.46V
* 75kΩ Internal Input Pulldown Resistors
* Direct Replacement for On Semiconductor MC10E131 & MC100E131

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