Description
The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter. Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits usable as programmable counters. The circuits can also be used as 4-bit latches, loading data from the Parallel Data inputs when PL is LOW and storing the data when PL is HIGH.

Features
*Low Power Consumption — Typically 80 mW
*High Counting Rates — Typically 70 MHz
*Choice of Counting Modes — BCD, Bi-Quinary, Binary
*Asynchronous Presettable
*Asynchronous Master Reset
*Easy Multistage Cascading
*Input Clamp Diodes Limit High Speed Termination Effects

SN74LS196, SN54LS197, SN74LS197

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General Description
The CD4020BM/CD4020BC, CD4060BM/CD4060BC are 14-stage ripple carry binary counters, and the CD4040BM/ CD4040BC is a 12-stage ripple carry binary counter. The counters are advanced one count on the negative transition of each clock pulse. The counters are reset to the zero state by a logical ``1'' at the reset input independent of clock.

Features
ㅁ Wide supply voltage range 1.0V to 15V
ㅁ High noise immunity 0.45 VDD (typ.)
ㅁ Low power TTL Fan out of 2 driving 74L
   compatibility or 1 driving 74LS
ㅁ Medium speed operation 8 MHz typ. at VDD e 10V
ㅁ Schmitt trigger clock input

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General Description
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the 'LS90 and divideby- eight for the 'LS93. All of these counters have a gated zero reset and the LS90 also has gated set-to-nine inputs for use in BCD nine's complement applications. To use their maximum count length (decade or four bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide- by-ten count can be obtained from the 'LS90 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.

Features
ㅁ Typical power dissipation 45 mW
ㅁ Count frequency 42 MHz

DM74LS90M DM74LS93M DM74LS90N DM74LS93N
TAG Counters

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