Description
Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-touse, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes. The XCFxxP version includes 32-Mbit,
16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes. A summary of the Platform Flash PROM family members and supported features is shown in Table 1.

Features
*In-System Programmable PROMs for Configuration of Xilinx® FPGAs
*Low-Power Advanced CMOS NOR Flash Process
*Endurance of 20,000 Program/Erase Cycles
*Operation over Full Industrial Temperature Range (–40°C to +85°C)
*IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
*JTAG Command Initiation of Standard FPGA Configuration
*Cascadable for Storing Longer or Multiple Bitstreams
*Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
*I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V
*Design Support Using the Xilinx Alliance ISE® and Foundation™ ISE Series Software Packages
*XCF01S/XCF02S/XCF04S
-3.3V Supply Voltage
-Serial FPGA Configuration Interface (up to 33 MHz)
-Available in Small-Footprint VO20 and VOG20 Packages
*XCF08P/XCF16P/XCF32P
-1.8V Supply Voltage
-Serial or Parallel FPGA Configuration Interface(up to 33 MHz)
-Available in Small-Footprint VO48, VOG48, FS48, and FSG48 Packages
-Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for
Configuration
-Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology

XCF02S, XCF04S, XCF08P, XCF16P, XCF32P

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Description
Xilinx introduces the QPro™ XQ18V04 Military Grade 4Mbit in-system programmable configuration Flash PROM. The XQ18V04 is a 3.3V rewritable PROM that provides a reliable non-volatile method for storing large Xilinx FPGA configuration bitstreams used in systems that
require operation over the full military temperature range.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in SelectMAP mode (Slave), an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data
is available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are
interconnected. The XQ18V04 is compatible and can be cascaded with other configuration PROMs such as the XQR1701L and XQR17V16 one-time programmable configuration
PROMs.

Features
*Operating Temperature Range: –55° C to +125°C
*Low-power advanced CMOS FLASH process memory cells immune to static single event upset
*In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
*IEEE Std 1149.1 boundary-scan (JTAG) support
*Cascadable for storing longer or multiple bitstreams
*Dual configuration modes
- Serial Slow/Fast configuration (up to 20 MHz)
- Parallel (up to 160 Mbps at 20 MHz)
*5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
*3.3V or 2.5V output capability
*Available in plastic VQ44 packaging only
*Design support using the Xilinx Alliance Series™ and Xilinx Foundation Series™ software packages
*JTAG command initiation of standard FPGA configuration

XQV300, XQV600, XQV1000

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Description
The AT17FxxA Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays.
The AT17FxxA Series device is packaged in the 8-lead LAP and 20-lead PLCC, see Table 1. The AT17FxxA Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices.
The AT17FxxA Series Configurators can be programmed with industry-standard programmers,
Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Features
* Programmable 16, 777, 216 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)
* 3.3V Output Capability
* 5V Tolerant I/O Pins
* Program Support using the Atmel ATDH2200E System or Industry Third Party Programmers
* In-System Programmable (ISP) via 2-wire Bus
* Simple Interface to SRAM FPGAs
* Compatible with Atmel AT40K and AT94K Devices, Altera FLEX®, Excalibur™, Stratix™, Cyclone™ and APEX™ Devices
* Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
* Low-power CMOS FLASH Process
* Available in 8-lead LAP and 20-lead PLCC Packages
* Emulation of Atmel’s AT24CXXX Serial EEPROMs
* Low-power Standby Mode
* Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System Reconfiguration
* Fast Serial Download Speeds up to 33 MHz
* Endurance: 10,000 Write Cycles Typical
* LHF Package Available (Lead and Halide Free)

AT17F16A-30CC
AT17F16A-30CI
AT17F16A-30CU
AT17F16A-30JC
AT17F16A-30JI
AT17F16A-30JU

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Description
 Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs.
Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin.
New data is available a short access time after each rising clock edge.
The FPGA generates the appropriate number of clock pulses to complete the configuration.
When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM.
When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA.
After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins.
New data is available a short access time after each rising clock edge.
The data is clocked into the FPGA on the following rising edge of the CCLK.
A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device.
The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.
All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.

Features
* In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs
- Endurance of 20,000 Program/Erase Cycles
- Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)
* IEEE Std 1149.1 Boundary-Scan (JTAG) Support
* JTAG Command Initiation of Standard FPGA Configuration
* Simple Interface to the FPGA
* Cascadable for Storing Longer or Multiple Bitstreams
* Low-Power Advanced CMOS FLASH Process
* Dual Configuration Modes
- Serial Slow/Fast Configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
* 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
* 3.3V or 2.5V Output Capability
* Design Support Using the Xilinx ISE™ Foundation™ Software Packages
* Available in PC20, SO20, PC44, and VQ44 Packages
* Lead-Free (Pb-Free) Packaging

XC18V04
XC18V02
XC18V01
XC18V512

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