'Clocking' related articles 1

  1. 2009/04/04 XCR3064A - 64 Macrocell CPLD With Enhanced Clocking
The XCR3064A CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner™ CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 μA at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the patented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 1.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.0 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
The XCR3064A CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).
The XCR3064A CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BPMicrosystems, SMS, and others. The XCR3064A also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported.

*Industry's first TotalCMOS™ PLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
*3V, In-System Programmable (ISP) using a JTAG interface
-On-chip superVoltage generation
-ISP commands include: Enable, Erase, Program, Verify
-Supported by multiple ISP programming platforms
-Four pin JTAG interface (TCK, TMS, TDI, TDO)
-JTAG commands include: Bypass, Idcode
*High speed pin-to-pin delays of 7.5 ns
*Ultra-low static power of less than 100 μA
*5V tolerant I/Os to support mixed Voltage systems
*100% routable with 100% utilization while all pins and all macrocells are fixed
*Deterministic timing model that is extremely simple to use
*Up to 12 clocks with programmable polarity at every macrocell
*Support for complex asynchronous clocking
*Innovative XPLA™ architecture combines high speed with extreme flexibility
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Logic expandable to 37 product terms
*Advanced 0.35μ E2CMOS process
*Security bit prevents unauthorized access
*Design entry and verification using industry standard and Xilinx CAE tools
*Reprogrammable using industry standard device programmers
*Innovative Control Term structure provides either sum terms or product terms in each logic block for:
-Programmable 3-state buffer
-Asynchronous macrocell register preset/reset
-Up to two asynchronous clocks
*Programmable global 3-state pin facilitates `bed of nails' testing without using logic resources
*Available in PLCC, VQFP, and Chip Scale BGA packages
*Industrial grade operates from 2.7V to 3.6V

XCR3064A-7VQ44C, XCR3064A-10VQ44C, XCR3064A-12VQ44C, XCR3064A-7PC44C

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