The Si5010 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data rates. DSPLL® technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance in the application.
The Si5010 represents an industry-leading combination of low-jitter, low-power, and small size for high-speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40 to 85 °C).

Complete CDR solution includes the following:
*Supports OC-12/3, STM-4/1
*Low power, 293 mW (TYP OC-12)
*Small footprint: 4x4 mm
*DSPLL™ eliminates external loop filter components
*3.3 V tolerant control inputs
*Exceeds All SONET/SDH jitter specifications
*Jitter generation 1.6 mUIrms (typ)
*Device powerdown
*Loss-of-lock indicator
*Single 2.5 V supply

*SONET/SDH/ATM routers
*Add/drop multiplexers
*Digital cross connects
*Board level serial links
*SONET/SDH test equipment
*Optical transceiver modules
*SONET/SDH regenerators

Si5010-BM, Si5010-GM

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The IDT5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9306 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL.
The IDT5T9306 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

*Guaranteed Low Skew < 25ps (max)
*Very low duty cycle distortion < 125ps (max)
*High speed propagation delay < 1.75ns (max)
*Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
*Up to 1GHz operation
*Selectable inputs
*Hot insertable and over-voltage tolerant inputs
*3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface
*Selectable differential inputs to six LVDS outputs
*Power-down mode
*2.5V VDD
*Available in VFQFPN package

*Clock distribution

TAG Buffer, Clock, LVDS

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The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM (nvSRAM) with a full featured real time clock in a reliable, monolithic integrated circuit.
The 1 Mb nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell.
The SRAM provides the fast access and cycle times, ease of use and unlimited read and write endurance of a normal SRAM. Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control.
The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programmable watchdog timer for processor control.

*nvSRAM Combined with Integrated Real Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor)
*Capacitor or Battery Backup for RTC
*25, 45 ns Read Access and Read/Write Cycle Time
*Unlimited Read/Write Endurance
*Automatic nonvolatile STORE on Power Loss
*Nonvolatile STORE Under Hardware or Software Control
*Automatic RECALL to SRAM on Power Up
*Unlimited RECALL Cycles
*200K STORE Cycles
*20-Year nonvolatile Data Retention
*Single 3 V +20%, -10% Power Supply
*Commercial and Industrial Temperatures
*48-pin 300-mil SSOP Package (RoHS-Compliant)

TAG Clock, nvsram

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The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.

*Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
*Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
*Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz)
*Meets OC-192 GR-253-CORE jitter specifications
*Dual clock inputs w/manual or automatically controlled hitless switching
*Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)
*Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236)
*LOL, LOS, FOS alarm outputs
*Digitally-controlled output phase adjust
*I2C or SPI programmable
*On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation
*Small size: 6 x 6 mm 36-lead QFN
*Pb-free, ROHS compliant

*SONET/SDH OC-48/OC-192 line cards
*GbE/10GbE, 1/2/4/8/10GFC line cards
*ITU G.709 and custom FEC line cards
*Optical modules
*Wireless basestations
*Data converter clocking
*SONET/SDH + PDH clock synthesis
*Test and measurement

Si5326A-B-GM, Si5326B-B-GM, Si5326C-B-GM

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The ICS557-05A is a spread-spectrum clock generator that supports PCI-Express requirements. It is used in PC or embedded systems to substantially reduce electro-magnetic interference (EMI). The device provides four differential HCSL or LVDS high-frequency outputs with spread spectrum capability. The output frequency and spread type are selectable using external pins.

*Packaged in 20-pin TSSOP
*Available in RoHS 5 (green) or RoHS 6 (green and lead free) complaint package
*Supports PCI-Express applications
*Four differential spread spectrum clock outputs
*Spread spectrum for EMI reduction
*Uses external 25 MHz clock or crystal input
*Power down pin turns off chip
*OE control tri-states outputs
*Spread and frequency selection via external pins
*Spread Bypass option available
*Industrial temperature range available

ICS557G-05A, ICS557G-05AT, ICS557G-05ALF, ICS557G-05ALFT

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The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs.

*2.5V or 3.3V operation
*200-MHz clock support
*LVPECL or LVCMOS/LVTTL clock input
*LVCMOS/LVTTL compatible outputs
*15 clock outputs: drive up to 30 clock lines
*1X and 1/2X configurable outputs
*Output three-state control
*350 ps maximum output-to-output skew
*Pin compatible with MPC949, MPC9449
*Available in Commercial and Industrial temperature range
*52-pin TQFP package

CY29949AXI, CY29949AXIT, CY29949AXC, CY29949AXCT

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The AMS222 is a low-cost, oscillator intended to be used as an external clock for low-frequency applications. The device consists of a resistor-programmed oscillator with complementary output stage. An external resistor allows for output frequency range to be adjusted from 10kHz to 6MHz. The complimentary output stage is very useful in paralleling, switching regulators for doubling the output current. AMS222 is offered in SOT-23 5-leads package.

*Low-Cost, Oscillator/Clock Generator
*Simple User Programming
*Output frequency programmable from 10 kHz to 6MHz
*2.7 to 15V Single-Supply Operation
*Output frequency tolerance <1%
*Complementary output signal
*Break before make output signal

*Switch-Mode Power Supplies
*Embedded Microcontrollers
*Industrial Controls
*Automotive Applications


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The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/port cards. This device phase locks to one of three reference inputs in the range of 19.44 MHz and generates four synchronous clock outputs that can be independently configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock). Silicon Laboratories DSPLL™ technology delivers phase-locked loop (PLL) functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. The on-chip reference monitoring and clock switching functions support Stratum 3/3E and SMC compatible clock switching with excellent output phase transient characteristics. FEC rates are supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios. The Si5364 establishes a new standard in performance and integration for ultra-low jitter clock generation. It operates from a single 3.3 V supply.

*Ultra-low jitter clock outputs with jitter generation as low as 0.3 psRMS
*No external components (other than a resistor and standard bypassing)
*Up to three clock inputs
*Four independent clock outputs at 19, 155, or 622 MHz
*Stratum 3, 3E, and SMC compatible
*Digital hold for loss-of-input clock
*Automatic or manually-controlled hitless switching between clock inputs
*Revertive/non-revertive switching
*Loss-of-signal and frequency offset alarms for each clock input
*Support for forward and reverse FEC clock scaling
*8 kHz frame sync output
*Low power
*Small size (11x11 mm)

*SONET/SDH line/port cards
*Terabit routers
*Core switches
*Digital cross connects


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The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as insystem programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

*Three internal PLLs
*Internal non-volatile EEPROM
*JTAG and FAST mode I2C serial interfaces
*Input Frequency Ranges: 1MHz to 400MHz
*Output Frequency Ranges:
-LVTTL: up to 200MHz
-LVPECL/ LVDS: up to 500MHz
*Reference Crystal Input with programmable oscillator gain and programmable linear load capacitance
-Crystal Frequency Range: 8MHz to 50MHz
*Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
*10-bit post-divider blocks
*Fractional Dividers
*Two of the PLLs support Spread Spectrum Generation capability
*I/O Standards:
-Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
-Inputs - 3.3V LVTTL/ LVCMOS
*Programmable Slew Rate Control
*Programmable Loop Bandwidth Settings
*Programmable output inversion to reduce bimodal jitter
*Redundant clock inputs with glitchless auto and manual switchover options
*JTAG Boundary Scan
*Individual output enable/disable
*Power-down mode
*3.3V VDD
*Available in TQFP and VFQFPN packages


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General Description
CY25562 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic interference (EMI) found in today’s high speed digital electronic systems.
CY25562 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is greatly reduced.
This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading system performance.
CY25562 is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Table 1 for programming details.
CY25562 is intended for applications with a reference frequency in the range of 50 to 200 MHz.
A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing.
CY25562 is available in an eight-pin SOIC package with a 0 to 70°C operating temperature range.
Refer to CY25561 for applications with lower drive requirements, and CY25560 with lower drive and frequency requirements.

*50 to 200 MHz Operating Frequency Range
*Wide range of spread selections: 9
*Accepts Clock and Crystal Inputs
*Low Power Dissipation
-70 mW Typ (Fin = 65 MHz)
*Frequency Spread Disable Function
*Center Spread Modulation
*Low Cycle-to-cycle Jitter
*8-pin SOIC Package

*High resolution VGA controllers
*LCD panels and monitors
*Workstations and servers

CY25562SXC, CY25562SXCT

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