Description
The XCR3064A CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner™ CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 μA at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the patented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 1.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.0 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
The XCR3064A CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).
The XCR3064A CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BPMicrosystems, SMS, and others. The XCR3064A also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported.

Features
*Industry's first TotalCMOS™ PLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
*3V, In-System Programmable (ISP) using a JTAG interface
-On-chip superVoltage generation
-ISP commands include: Enable, Erase, Program, Verify
-Supported by multiple ISP programming platforms
-Four pin JTAG interface (TCK, TMS, TDI, TDO)
-JTAG commands include: Bypass, Idcode
*High speed pin-to-pin delays of 7.5 ns
*Ultra-low static power of less than 100 μA
*5V tolerant I/Os to support mixed Voltage systems
*100% routable with 100% utilization while all pins and all macrocells are fixed
*Deterministic timing model that is extremely simple to use
*Up to 12 clocks with programmable polarity at every macrocell
*Support for complex asynchronous clocking
*Innovative XPLA™ architecture combines high speed with extreme flexibility
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Logic expandable to 37 product terms
*Advanced 0.35μ E2CMOS process
*Security bit prevents unauthorized access
*Design entry and verification using industry standard and Xilinx CAE tools
*Reprogrammable using industry standard device programmers
*Innovative Control Term structure provides either sum terms or product terms in each logic block for:
-Programmable 3-state buffer
-Asynchronous macrocell register preset/reset
-Up to two asynchronous clocks
*Programmable global 3-state pin facilitates `bed of nails' testing without using logic resources
*Available in PLCC, VQFP, and Chip Scale BGA packages
*Industrial grade operates from 2.7V to 3.6V

XCR3064A-7VQ44C, XCR3064A-10VQ44C, XCR3064A-12VQ44C, XCR3064A-7PC44C

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Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.
A total of two function blocks provide 750 usable gates.
Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz.

Features
*Lowest power 32 macrocell CPLD
*5.0 ns pin-to-pin logic delays
*System frequencies up to 200 MHz
*32 macrocells with 750 usable gates
*Available in small footprint packages
-48-ball CS BGA (36 user I/O pins)
-44-pin VQFP (36 user I/O)
-44-pin PLCC (36 user I/O)
*Optimized for 3.3V systems
-Ultra-low power operation
-5V tolerant I/O pins with 3.3V core supply
-Advanced 0.35 micron five layer metal EEPROM process
-Fast Zero Power™ (FZP) CMOS design technology
*Advanced system features
-In-system programming
-Input registers
-Predictable timing model
-Up to 23 available clocks per function block
-Excellent pin retention during design changes
-Full IEEE Standard 1149.1 boundary-scan (JTAG)
-Four global clocks
-Eight product term control terms per function block
*Fast ISP programming times
*Port Enable pin for dual function of JTAG ISP pins
*2.7V to 3.6V supply voltage at industrial temperature range
*Programmable slew rate control per macrocell
*Security bit prevents unauthorized access
*Refer to XPLA3 family data sheet (DS012) for architecture description

XCR3032XL-5VQ44C
XCR3032XL-10VQ44C

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Description
The CoolRunner-II Automotive 128-macrocell device is designed for both high performance and low power applications.
This lends power savings to high-end communication equipment and high speed to battery operated devices.
Due to the low power stand-by and dynamic operation, overall system reliability is improved
This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each Function Block.
The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch.
There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis.
Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.
A Schmitt-trigger input is available on a per input pin basis.
In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis.
This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.
Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.

Features
* AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
* Guaranteed to meet full electrical specifications over TA = -40°C to +105°C with TJ Maximum = +125°C (Q-grade)
* Optimized for 1.8V systems
* Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
* Available in the following package options
- 100-pin VQFP with 80 user I/O
- 132-ball CP (0.5mm) BGA with 100 user I/O
- Pb-free only for all packages

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Description
 The CoolRunner™-II Automotive 32-macrocell device is designed for both high performance and low power applications.
This lends power savings to high-end communication equipment and high speed to battery operated devices.
Due to the low power stand-by and dynamic operation, overall system reliability is improved.
This device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each Function Block.
The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch.
There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis.
Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.
A Schmitt trigger input is available on a per input pin basis.
In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
The CoolRunner-II Automotive 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33.
This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O banking.
Two I/O banks are available on the CoolRunner-II Automotive 32-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

Features
• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
• Guaranteed to meet full electrical specifications over TA = -40° C to +105° C with TJ Maximum = +125° C (Q-grade)
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
• Available in Pb-free 44-pin VQFP with 33 user I/O
• Advanced system features
- Fastest in system programming
 · 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
 · Optional DualEDGE triggered registers
- Global signal options with macrocell control
 · Multiple global clocks with phase selection per macrocell
 · Multiple global output enables
 · Global set/reset
- Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
- PLA architecture
 · Superior pinout retention
 · 100% product term routability across function block
- Hot pluggable
Refer to the CoolRunner™-II Automotive CPLD family data sheet for architecture description.

XA2C32A-6VQG44I
XA2C32A-7VQG44Q

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Features
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS FastFLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package

Description
The XC9572XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications communications and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview.
TAG CPLD

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