DESCRIPTION
The CAT6219 is a 500mA CMOS low dropout regulator that provides fast response time during load current and line voltage changes.
The quick-start feature allows the use of an external bypass capacitor to reduce the overall output noise without affecting the turn-on time of just 150μs.
With zero shutdown current and low ground current of 55μA typical, the CAT6219 is ideal for batteryoperated devices with supply voltages from 2.3V to 5.5V. An internal under voltage lockout circuit disables the output at supply voltages under 2.15V typical.
The CAT6219 offers 1% initial accuracy and low dropout voltage, 300mV typical at 500mA. Stable operation is provided with a small value ceramic capacitor, reducing required board space and component cost.
Other features include current limit and thermal protection.
The LDO is available in fixed and adjustable output in the low profile (1mm max height) 5-lead TSOT23 and in the 6-pad 2mm x 2mm TDFN packages.

FEATURES
*Guaranteed 500mA peak output current
*Low dropout voltage of 300mV typical at 500mA
*Stable with ceramic output capacitor
*External 10nF bypass capacitor for low noise
*Quick-start feature
*Under voltage lockout
*No-load ground current of 55μA typical
*Full-load ground current of 85μA typical
*±1.0% initial accuracy (VOUT ≥ 2.0V)
*±2.0% accuracy over temperature (VOUT ≥ 2.0V)
*“Zero” current shutdown mode
*Current limit and thermal protection
*5-lead TSOT-23 and 6-pad TDFN packages

APPLICATIONS
*Cellular phones
*Battery-powered devices
*Consumer Electronics

CAT6219-125TD-GT3, CAT6219-180TD-GT3, CAT6219-250TD-GT3

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Product Description
Pericom Semiconductor’s PI74LCX series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology, achieving industry leading speed grades.
The PI74LCX646 and PI74LCX652 are designed with a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The PI74LCX652 utilizes GAB and GBA signals to control the transceiver functions. The PI74LCX646 uses the enable control (G) and direction pins (DIR) to control the transceiver functions. SAB and SBA control pins are used to select either real-time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between real-time and
stored data. A low input level selects real-time data and a high selects stored data.
The PI74LCX646 and PI74LCX652 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system.

Product Features
*Functionally compatible with FCT3, LVT, and 74 series 646 and 652 families of products
*Tri-State outputs
*5V Tolerant inputs and outputs
*2.0V-3.6V VCC supply operation
*Balanced sink and source output drives (24 mA)
*Low ground bounce outputs
*Supports live insertion
*ESD Protection exceeds 2000V, Human Body Model 200V, Machine Model
*Packages available:
– 24-pin 209-mil wide plastic SSOP (H)
– 24-pin 173-mil wide plastic TSSOP (L)
– 24-pin 150-mil wide plastic QSOP (Q)
– 24-pin 300-mil wide plastic SOIC (S)

PI74LCX652

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Description
The DG401/403/405 monolithic analog switches were designed to provide precision, high performance switching of analog signals. Combining low power (0.35 W, typ) with high speed (tON: 100 ns, typ), the DG401 series is ideally suited for portable and battery powered industrial and military applications.
Built on the Siliconix proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the SPDT configurations. An epitaxial layer prevents latchup.
Each switch conducts equally well in both directions when on, and blocks up to 30 V peak-to-peak when off. On-resistance is very flat over the full 15-V analog range, rivaling JFET performance without the inherent dynamic range limitations.
The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams.

Features
*44-V Supply Max Rating
*±15-V Analog Signal Range
*On-Resistance—rDS(on): 20 Ω
*Low Leakage—ID(on): 40 pA
*Fast Switching—tON: 100 ns
*Ultra Low Power Requirements—PD: 0.35 μ W
*TTL, CMOS Compatible
*Single Supply Capability

Benefits
*Wide Dynamic Range
*Low Signal Errors and Distortion
*Break-Before-Make Switching Action
*Simple Interfacing

Applications
*Audio and Video Switching
*Sample-and-Hold Circuits
*Battery Operation
*Test Equipment
*Hi-Rel Systems
*PBX, PABX

DG403, DG405, DG401DJ, DG403DJ, DG405DJ
TAG CMOS, Switches

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DESCRIPTION
The LZ34B1B is a 1/4-type (4.5 mm) solid-state color image sensor that consists of PN photodiodes and CMOS (Complementary Metal Oxide Semiconductor) devices. The sensor further includes a timing generator (TG), a correlated double sampling (CDS) circuit, an auto gain control (AGC) circuit and an analog-to-digital converter (ADC) circuit. With approximately 350 000 pixels (703 horizontal x 499 vertical), the sensor provides a stable digital color image with extremely low power consumption.

FEATURES
*Progressive scan
*Square pixel
*Compatible with VGA standard
*Number of image pixels : 655 (H) x 493 (V)
*Number of optical black pixels
–Horizontal : 24 front and 24 rear
–Vertical : 3 front and 3 rear
*Pixel pitch : 5.6 μm (H) x 5.6 μm (V)
*R, G, and B primary color mosaic filters
*Image inversion function (horizontally and/or vertically)
*Available for two types of power save mode
–AGC and AD circuits become power-off with serial data
–All circuits become power-off with STBY pin
*Monitoring mode
*Analog output and 8-bit digital output
*Variable gain control (3 to 30 dB)
*Variable electronic focal plane shutter (1/15 to 1/7 875 s)
*Single +2.8 V power supply
*Package : 36-pin LCC (N-LCC036-S425B)
TAG CMOS, Sensor

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GENERAL DESCRIPTION
The K6T2008V2A and K6T2008U2A families are fabricated by SAMSUNG¢s advanced CMOS process technology. The family support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery backup operation with low data retention current.

FEATURES
*Process Technology: TFT
*Organization: 256Kx8
*Power Supply Voltage
-K6T2008V2A Family: 3.0V~3.6V
-K6T2008U2A Family: 2.7V~3.3V
*Low Data Retention Voltage: 2V(Min)
*Three State Outputs
*Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F 48-FBGA-6.00x7.00

K6T2008V2A-B, K6T2008U2A-B, K6T2008V2A-F, K6T2008U2A-F

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Outline
This IC is a PWM controlled switching regulator developed using the CMOS process. Low ripple and high efficiency of 83% typ. (MM3005E) are achieved through PWM control. Further, output voltage is high precision output ±2.4%.

Features
*Ultra low consumption current 17.2μA typ. (during operation) (MM3005E)
*High efficiency 83% typ. (MM3005E)
*High precision output voltage ±2.4%
*Wide operating temperature range -30°C~+85°C
*Output voltage 2~5.5V (0.1V can be set in 0.1V steps)

Applications
*Mobile phones, PHS
*Portable MD
*Other battery-operated portable equipment

MM3006, MM3007, MM3008, MM3009, MM3010

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GENERAL DESCRIPTION
The ICS841S01 is a PLL-based clock generator specifically designed for PCI_Express™Clock
Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating.
The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%.
The ICS841S01 is available in both standard and lead-free 16-Lead TSSOP packages.

FEATURES
*One 0.7V current mode differential HCSL output pair
*Crystal oscillator interface, 25MHz
*Output frequency: 100MHz
*RMS period jitter: 3ps (maximum)
*Cycle-to-cyle jitter: 35ps (maximum)
*I2C support with readback capabilities up to 400kHz
*Spread Spectrum for electromagnetic interference (EMI) reduction
*3.3V operating supply mode
*0°C to 70°C ambient operating temperature
*Available in both standard (RoHS 5) and lead-free (RoHS 6) packages

ICS841S01BG, ICS841S01BGT, ICS841S01BGLF, ICS841S01BGLFT

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General Description
The HT25LC512 is a 512K-bit OTP ROM of which function and pin assignment are compatible with AT25F512 and can directly replace the AT25F512 for cost down purposes when the memory in the system is just read only. There are 512K bits of memory which are organized as 65536 words of 8 bits each. The HT25LC512 uses a serial interface to sequentially access its data.
The simple serial interface facilitates hardware layout, increase system reliability, minimize switching noise, and reduce package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low
voltage, and low power consumption are essential. The device operates at clock frequencies up to 10MHZ. The HT25LC512 is enabled through the chip select pin CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). The HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.

Features
*Operating voltage: 2.7V~3.6V
*Programming voltage
- VPP=12.5V#0.2V
- VCC=6.0V#0.2V
*512K-bit OTP ROM, access command compatible with AT25F512
*64K$8-bit organization
*12MHz max. clock frequency @VCC=2.7V, 15MHz max. clock frequency @VCC=3.0V
*Serial interface architecture
*Serial Peripheral Interface (SPI) compatible - modes 0 and 3
*CMOS and TTL compatible inputs and outputs
*Pin assignment compatible with AT25F512
*Commercial temperature range (0%C to +70%C)
*8-pin SOP package

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General Description
The AP7217A low-dropout linear regulator operates from a 3.3V to 5.5V supply and delivers a guaranteed 600mA (min) continuous load current.
The high-accuracy output voltage is preset to an internally trimmed voltage. An active-low open-drain reset output remains asserted for at least 200ms (TYP) after output voltage reaches regulation.
The space-saving SOP-8L and SOP-8L-EP packages are suitable for “pocket” and hand-held application.

Features
*Very Low Dropout Voltage
*Low Current Consumption: Typ. 50μA
*Output Voltage: 3.3V
*Guaranteed 600mA (min) Output
*Input Range up to 5.5V
*Current Limiting
*Stability with Low ESR Capacitors
*Thermal shutdown Protection
*Low Temperature Coefficient
*SOP-8L and SOP-8L-EP: Available in “Green” Molding Compound (No Br, Sb)
*Lead Free Finish/ RoHS Compliant (Note 1)

Applications
*HD/ Blue Ray DVD & MP3/4 Players
*CD and MP3 Players
*Cellular and PCS Phones
*Digital Still Camera
*Hand-Held Computers

AP7217A-XXS, AP7217A-XXSP
TAG CMOS, LDO

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General Description
The A29L160 is a 16Mbit, 3.0 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L160 is offered in 48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L160 can also be programmed in standard EPROM programmers.
The A29L160 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L160 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L160 also offers the ability to program in the Erase Suspend mode. The standard A29L160 offers access times of 70, 90 and 120ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE ) and output enable (OE ) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The A29L160 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L160 is fully erased when shipped from the factory. The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

Features
*Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors
*Access times:
- 70/90/120 (max.)
*Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
*Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors
*Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple program command sequence
*Top or bottom boot block configurations available
*Embedded Algorithms
- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
- Embedded Program algorithm automatically writes and verifies data at specified addresses
*Typical 100,000 program/erase cycles per sector
*20-year data retention at 125°C
- Reliable operation for the life of the system
*CFI (Common Flash Interface) compliant
- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
*Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply Flash memory standard
- Superior inadvertent write protection
*Data Polling and toggle bits
- Provides a software method of detecting completion of program or erase operations
*Ready / BUSY pin (RY / BY)
- Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP)
*Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
*Hardware reset pin (RESET )
- Hardware method to reset the device to reading array data
*Package options
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
- All Pb-free (Lead-free) products are RoHS compliant

A29L160TM-70, A29L160TV-70, A29L160TV-70F, A29L160TG-70, A29L160TM-90, A29L160TV-90, A29L160TG-90, A29L160TM-120, A29L160TV-120, A29L160TG-120

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